Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 941-946

  Zhang, Lizheng ^a   Tsai, Jengliang ^a   Chen, Weijen ^a   Hu, Yuhen ^a   Chen, Charlie Chung Ping ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ITERATIVE METHODS; MONTE CARLO METHODS; RANDOM PROCESSES; STATISTICAL METHODS; VLSI CIRCUITS;

BENCHMARK CIRCUITS; EXPONENTIAL COMPLEXITY; FEEDBACK LOOPS; STATISTICAL TIMING ANALYSIS;

FEEDBACK CONTROL;

EID: 33748611879     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118511     Document Type: Conference Paper

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