Timing analysis algorithm for circuits with level-sensitive latches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 5, 1996, Pages 535-543

  Lee, Jin fuw ^a   Tang, Donald T ^a   Wong, C K ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SOFTWARE; DELAY CIRCUITS; FINITE AUTOMATA; FLIP FLOP CIRCUITS; TIMING CIRCUITS;

BELLMAN-FORD METHOD; LEVEL SENSITIVE LATCHES; TIMING ANALYSIS ALGORITHMS; TIMING SIGNAL PATHS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030145050     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.506140     Document Type: Article

References (11)

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