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Volumn , Issue , 2004, Pages 619-625

Clock schedule verification under process variations

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SCHEDULE; CLOCK SKEW; GLOBAL TIME REFERENCE; PROCESS VARIATIONS;

EID: 16244418078     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382650     Document Type: Conference Paper
Times cited : (6)

References (16)
  • 2
    • 0348040110 scopus 로고    scopus 로고
    • Block-based static timing analysis with uncertainty
    • San Jose,CA, November
    • A. Devgan and C. Kashyap. Block-based static timing analysis with uncertainty. In Proc. Intl. Conf. on Computer-Aided Design, pages 607-614, San Jose,CA, November 2003.
    • (2003) Proc. Intl. Conf. on Computer-aided Design , pp. 607-614
    • Devgan, A.1    Kashyap, C.2
  • 4
    • 0348040085 scopus 로고    scopus 로고
    • Statistical timing analysis for intra-die process variations with spatial correlations
    • San Jose,CA, November
    • A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proc. Intl. Conf. on Computer-Aided Design, pages 900-907, San Jose,CA, November 2003.
    • (2003) Proc. Intl. Conf. on Computer-aided Design , pp. 900-907
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3
  • 5
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single pert-like traversal
    • San Jose,CA, November
    • H. Chang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In Proc. Intl. Conf. on Computer-Aided Design, pages 621-625, San Jose,CA, November 2003.
    • (2003) Proc. Intl. Conf. on Computer-aided Design , pp. 621-625
    • Chang, H.1    Sapatnekar, S.S.2
  • 6
    • 84893769730 scopus 로고
    • On the performance of level-clocked circuits
    • C. Ebeling and B. Lockyear. On the performance of level-clocked circuits. In Advanced Research in VLSI, pages 242-356, 1995.
    • (1995) Advanced Research in VLSI , pp. 242-356
    • Ebeling, C.1    Lockyear, B.2
  • 12
    • 0026961616 scopus 로고
    • Computing optimal clock schedules
    • Anaheim, CA, June
    • T. G. Szymanski. Computing optimal clock schedules. In Proc. of the Design Automation Conf., pages 399-404, Anaheim, CA, June 1992.
    • (1992) Proc. of the Design Automation Conf. , pp. 399-404
    • Szymanski, T.G.1
  • 14
    • 0029720911 scopus 로고    scopus 로고
    • Optimal clock skew scheduling tolerant to process variations
    • Las Vegas, NV, June
    • J. L. Neves and E. G. Friedman. Optimal Clock Skew Scheduling Tolerant to Process Variations. In Proc. of the Design Automation Conf., pages 623-628, Las Vegas, NV, June 1996.
    • (1996) Proc. of the Design Automation Conf. , pp. 623-628
    • Neves, J.L.1    Friedman, E.G.2
  • 16
    • 0001310038 scopus 로고
    • The greatest of a finite set of random variables
    • C. E. Clark. The Greatest of a Finite Set of Random Variables. Operations Research, 1961.
    • (1961) Operations Research
    • Clark, C.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.