Three-dimensional place and route for FPGAs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 773-778

  Ababei, Cristinel ^a   Mogal, Hushrav ^a   Bazargan, Kia ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DELAY CIRCUITS; SIMULATED ANNEALING;

3-D INTEGRATION; 3D TECHNOLOGY; CRITICAL PATHS; DETAILED ROUTING; FPGA INTEGRATION; PLACE AND ROUTE; PLACEMENT ALGORITHM; POTENTIAL BENEFITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 28344456185     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121015     Document Type: Conference Paper

References (19)

1. A. J. Alexander, J. P. Cohoon, Jared L. Colflesh, J. Karro, and G. Robins, "Three-Dimensional Field-Programmable Gate Arrays", Proc. Intl. ASIC Cortf., pp. 253-256, 1995.
2. A. J. Alexander, J. P. Cohoon, Jared L. Colflesh, J. Karro, E. L. Peters, and G. Robins, "Placement and Routing for Three-Dimensional FPGAs", Fourth Canadian Workshop on Field-Programmable Devices, pp. 11-18, 1996.
3. J. Karro and J. P. Cohoon, "A spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays", Ninth Great Lakes Symposium on VLSI. pp. 226-227, 1999.
4. V. Betz and J. Rose, "VPR: A New Packing Placement and Routing Tool for FPGA Research", Field-Programmable Logic App., pp. 213-222, 1997.
5. A. Marquardt, V. Betz, J. Rose, "Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density", FPGA. pp. 37-46, 1999.
6. S. Das, A. Chandrakasan, and R. Reif, "Design Tools for 3D Integrated Circuits", Proc. ACM/IEEE ASP-DAC. 2003.
7. S. Das, A. Chandrakasan, and R. Reif, "Three-Dimensional Integrated Circuits: Performance Design Methodology and CAD Tools", Proc. ACM/IEEE ISVLSI. 2003.
8. R. Reif, A. Fan, K. - N. Chen, and S. Das, "Fabrication Technologies for Three-Dimensional Integrated Circuits", Proc. International Symposium on Quality Electronic Design OSQD), 2002.
9. K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, and M. Koyanagi, "Three-dimensional shared memory fabricated using wafer stacking technology", in Technical Digest of the International Electron Devices Meeting, pp. 165-168, 2000.
10. A. Rahman, S. Das, A. Chandrakasan, and R. Reif, "Wiring Requirement and Three-Dimensional Integration of Field-Programmable Gate Arrays", Proc. ACM/IEEE SUP. 2001.
11. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multi-level Hypergraph Partitioning: Applications in VLSI Design", Proc. ACM/IEEEDAC. pp. 526-529, 1997.
12. Y. Deng and W. P. Maly, "Interconnect Characteristics of 2.5-D System Integration Scheme", Proc. ACM/IEEE ISPD,pp. 171-175, 2001.
13. P. Maidee, C. Ababei and K. Bazargan, "Fast Timing-driven Partitioning-based Placement for Island Style FPGAs", Proc. ACM/IEEE DAC. pp. 598-603, 2003.
14. Y-C. Ju, R.A. Saleh, "Incremental Techniques for the Identification of Statically Sensitizable Critical Paths", Proc. A CM/IEEE DAC. 1991.
15. B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach", Proc. ACM/IEEE ICCAD. pp. 86-89, 2003.
16. S. T. Obenaus.and T. H. Szymanski, "Gravity: Fast Placement for 3-D VLSI", ACM Trans, on Design Automation of Electronic Systems (TODAES), Vol. 8, No. 3, pp. 298-315, July 2003.
17. V. Betz, J. Rose, and A. Marquardt, "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, 1999.
18. C. Ebeling, L. McMurchie, S. A. Hauck, and S. Burns, "Placement and Routing Tools for the Trptych FPGA", IEEE Trans. VLSI Systems, Vol. 3, No. 4, pp. 472-483, Dec. 1995.
19. C. Ababei and K. Bazargan, "Non-contiguous Linear Placement for Reconftgurable Fabrics", Proc. Reconfigurable Architectures Workshop (RA W), 2004.