Global clustering-based performance-driven circuit partitioning

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 149-154

  Cong, Jason ^a   Wu, Chang ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clustering; Partitioning; Performance optimization; Retiming; VLSI CAD

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; DELAY CIRCUITS; OPTIMIZATION;

CIRCUIT PARTITIONING;

VLSI CIRCUITS;

EID: 0036376022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505388.505424     Document Type: Conference Paper

References (14)

1. Simultaneous circuit partitioning/clustering with retiming for performance optimization
2. Performance driven multi-level and multiway partitioning with retiming
3. A linear-time heuristic for improving network partitions
4. Multilevel hypergraph partitioning: Application in VLSI domain
5. Module clustering to minimize delay in digital networks
6. Retiming synchronous circuitry
7. Performance-driven partitioning using a replication graph approach
8. Performance-driven partitioning using retiming and replication
9. On clustering for minimum delay/area
10. Optimal clock period clustering for sequential circuits with retiming
11. Getting to the bottom of deep submicrion
12. Circuit clustering for delay minimization under area and pin constraints