Statistical timing driven partitioning for VLSI circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 1109-

  Ababei, Cristinel ^a   Bazargan, Kia ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CUT SIZE; DESIGN PROCESS; PARTITIONING ALGORITHMS; PERFORMANCE OPTIMIZATIONS; STATISTICAL TIMING; TIMING OPTIMIZATION;

EXHIBITIONS; VLSI CIRCUITS;

OPTIMIZATION;

EID: 84893771007     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998465     Document Type: Conference Paper

References (2)

1. C.M. Fiduccia, R.M. Mattheyses, 'A Linear-Time Heuristic for Improving Network Partitions', Proc. ACM/IEEE DAC, 1982.
2. M. Hashimoto, H. Onodera, 'A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis', IEICE Trans. Fundamentals, Dec. 2000.