Leakage power reduction in dual-Vdd and dual-Vth designs through probabilistic analysis of Vth variation

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 766-769

  Oruganti, Aswath ^a   Ranganathan, Nagarajan ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE POWER MINIMIZATION; LOW POWER CIRCUITS; PROBABILISTIC ANALYSIS;

NETWORKS (CIRCUITS); OPTIMIZATION; PROBABILISTIC LOGICS; THRESHOLD VOLTAGE;

LEAKAGE CURRENTS;

EID: 33748525606     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.110     Document Type: Conference Paper

References (13)

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