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Volumn 2005, Issue , 2005, Pages 625-630

Optimizing the thermal behavior of subarrayed data caches

Author keywords

[No Author keywords available]

Indexed keywords

CHIP LEAKAGE; MICROARCHITECTURES; ON-CHIP TEMPERATURE; PROCESSOR POWER CONSUMPTION;

EID: 33748524497     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.81     Document Type: Conference Paper
Times cited : (14)

References (22)
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  • 3
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  • 4
    • 0003281180 scopus 로고    scopus 로고
    • Dynamic thermal management for high-performance microprocessors
    • D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Proc. 7th HPCA'01, 2001.
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    • Brooks, D.1    Martonosi, M.2
  • 6
    • 1542296867 scopus 로고    scopus 로고
    • Memory hierarchy extensions to simplescalar 3.0
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    • D. Burger, A. Kagi, and M. S. Hrishikesh. Memory hierarchy extensions to simplescalar 3.0. Technical Report TR99-25, Department of Computer Sciences, The University of Texas at Austin, 2000.
    • (2000) Technical Report , vol.TR99-25
    • Burger, D.1    Kagi, A.2    Hrishikesh, M.S.3
  • 10
    • 3042601476 scopus 로고    scopus 로고
    • Stage-skip pipeline: A low power processor architecture using a decoded instruction buffer
    • M. Hiraki et al. Stage-skip pipeline: A low power processor architecture using a decoded instruction buffer. In Proc. ISLPED, 1996.
    • (1996) Proc. ISLPED
    • Hiraki, M.1
  • 13
    • 0033359006 scopus 로고    scopus 로고
    • Instruction fetch energy reduction using loop caches for embed ded applications with small tight loops
    • L. H. Lee, B. Moyer, and J. Arends. Instruction fetch energy reduction using loop caches for embed ded applications with small tight loops. In Proc. ISLPED, 1999.
    • (1999) Proc. ISLPED
    • Lee, L.H.1    Moyer, B.2    Arends, J.3
  • 16
    • 0003946111 scopus 로고    scopus 로고
    • An integrated cache timing and power model
    • Compaq Western Research Lab
    • G. Reinman and N. Jouppi. An integrated cache timing and power model. Technical report, Compaq Western Research Lab, 1999.
    • (1999) Technical Report
    • Reinman, G.1    Jouppi, N.2
  • 17
    • 0030685015 scopus 로고    scopus 로고
    • Thermal management system for high performance PowerPC microprocessors
    • San Jose California
    • H. Sanchez et al. Thermal management system for high performance PowerPC microprocessors. In Proceedings of COMPCON 97, San Jose California, 1997.
    • (1997) Proceedings of COMPCON 97
    • Sanchez, H.1
  • 19
    • 0001857537 scopus 로고    scopus 로고
    • Reducing power in high-performance microprocessors
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  • 20
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    • S.-H. Yang, M. D. Powell, B. Falsafi, K. Roy, and T. N. Vijaykumar. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance i-caches. In Proc. HPCA, 2001.
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  • 22
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    • Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects
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    • Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects. Technical report, Dept. of Computer Science, Univ. of Virginia, 2003.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.