Critical Area and Critical Levels Calculation in I.C. Yield Modeling

IEEE Transactions on Electron Devices

Volumn 35, Issue 2, 1988, Pages 158-166

  Gandemer, Sophie ^a   Tremintin, Bernard C ^a   Charlot, Jean Jacques ^b  

^a Matra Harris Semiconducteurs Ecole Nationale Superieure ^*  (France)

^b TELECOM PARISTECH   (France)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS - MASKS; MICROELECTRONICS - DEFECTS; SEMICONDUCTOR DEVICES - DENSITY;

AVERAGE DEFECT DENSITY; CRITICAL AREA AND CRITICAL LEVELS CALCULATION; IC YIELD MODEL; TOTAL CHIP AREA;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0023962947     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.2435     Document Type: Article

References (6)

1. B. T. Murphy, “Cost size optima for monolithic integrated circuits,” Proc. IEEE, vol. 52, pp. 1537-1545, Dec. 1964.
2. C. H. Stapper, “Defect density distribution for LSI yield calculations,” IEEE Trans. Electron Devices, vol. ED-20, pp. 655-657, July 1973.
3. A. V. Ferris-Prabhu, “Role of defect size distribution in yield modeling,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1727-1736, 1985.
4. C. H. Stapper, “Modeling of integrated circuit defect sensitivities,” IBM J. Res. Develop., vol. 27, no. 6, pp. 549-557, 1983.
5. —, “Modeling of defects in integrated circuit photolithographic patterns,” IBM J. Res. Develop., vol. 28, no. 4, pp. 461-475, 1984.
6. A. V. Ferris-Prabhu, “Modeling the critical area in yield forecasts,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 874-878, 1985.