VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 5, Issue 4, 1986, Pages 541-556

  Walker, Hank ^a   Director, Stephen W ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0001552625     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1986.1270225     Document Type: Article

References (32)

1. W. Maly, A. Strojwas, and S. Director, “Fabrication based statistical design of monolithic ICs,” in Proc. IEEE Int. Symp. Circuits and Systems, Apr. 1981, pp. 135–138.
2. S. Nassif, A. Strojwas, and S. Director, “FABRICS II: A statistically based IC fabrication process simulator,” IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 1, pp. 40–46, Jan. 1984.
3. W. Maly and A. Strojwas, “Statistical simulation of the IC manufacturing process,” IEEE Trans. Computer-Aided Design, vol. 1, no. 3, July 1982.
4. S. Nassif, A. Strojwas, and S. Director, “FABRICS II: A statistical simulator of the IC fabrication process,” in IEEE Int. Conf. Circuits and Computers Proc., Sept. 1982, pp. 289–301.
5. C. Stapper, “LSI yield modeling and process monitoring,” IBM J. Res. Develop., vol. 20, No. 3, pp. 228–234, May 1976.
6. R. Razdan and A. Strojwas, “Statistical design rule developer,” in IEEEInt. Conf Computer-Aided Design, Nov. 1985, pp. 315–317.
7. W. Maly, F. Ferguson, and J. Shen, “Systematic characterization of physical defects for fault analysis of MOS IC cells,” in IEEE Int. Test Conf. Proc., Oct. 1984, pp. 390–399.
8. J. Shen, W. Maly, and J. Ferguson, “Inductive fault analysis of MOS integrated circuits,” IEEE Design and Test of Computers, vol. 2, no. 6, pp. 13–26, Dec. 1985.
9. A. Gupta, “ACE: A circuit extractor,” in ACM IEEE 20th Design Automation Conf. Proc., June 1983.
10. J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G. Taylor, “The magic VLSI layout system,” IEEE Design and Test of Computers, vol. 2, no. 1, pp. 19–30, Feb. 1985.
11. C. Stapper, “Yield model for 256K RAMs and beyond,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1982, pp. 12–13.
12. T. Mangir, “Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI,” Proc. IEEE, vol. 72, pp. 690–708, June 1984.
13. viyfM. Elmasry, “Multidrain NMOS for VLSI logic design,” IEEE J. Solid-State Circuits, vol. SC-17, no. 2, pp. 409–411, Apr. 1982.
14. I. Sutherland, “The polygon package,” Silicon Structures Project 1438, Computer Sci. Dep. California Institute of Technology, Feb. 1978.
15. D. Lang, private communication.
16. H. Walker, “Yield simulation for integrated circuits,” Ph.D. dissertation, Computer Sci. Dep. Carnegie-Mellon Univ., 1986.
17. J. Bernard, “The I C yield problem: A tentative analysis for MOS/SOS circuits,” IEEE Trans. Electron Devices, vol. ED-25, pp. 939–944, Aug. 1978.
18. C. Stapper, “Modeling of integrated circuit defect sensitivities,” IBM J. Res. Develop., vol. 27, no. 6, pp. 549–557, Nov. 1983.
19. C. Stapper, “Modeling of defects in integrated circuit photolithographic patterns,” IBM J. Res. Develop., vol. 28. no. 4, pp. 461–475, July 1984.
20. C. Stapper, “The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions,” IBM J. Res. Develop., vol. 29, no. 1, pp. 87–97, Jan. 1985.
21. N. Johnson and S. Kotz, Discrete Distributions. Boston: Houghton Mifflin, 1969.
22. M. Ketchen, “Point defect yield model for wafer scale integration,” IEEE Circuits and Devices Magazine, vol. 1, no. 4, pp. 24–34, July 1985.
23. T. Yanagawa, “Influence of epitaxial mounds on the yield of integrated circuits,” Proc. IEEE, vol. 57, pp. 1621–1628, Sept. 1969.
24. W. Ham, “Yield-area analysis: Part I—A diagnostic tool for fundamental integrated-circuit process problems,” RCA Rev., vol. 39, no. 2, 231–249, June 1978.
25. H. Walker and S. Director, “VLASIC: A yield simulator for integrated circuits,” IEEE Int. Conf Computer-Aided Design Dig. Tech. Papers, Nov. 1985, pp. 318–320.
26. W. Maly, “Topics in point defect related yield losses,” Tech. Rep. CMUCAD-85-41, SRC-CMU Center for Computer-Aided Design, Dep. Elec. and Computer Eng., Carnegie-Mellon Univ., Feb. 1985.
27. C. Stapper, A. McLaren, and M. Dreckmann, “Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product,” IBM J. Res. Develop., vol. 24, no. 3, pp. 398-409, may 1980.
28. K. Saito and E. Arai, “Experimental analysis and new modeling of MOS LSI yield associated with the number of elements,” IEEE J. Solid-State Circuits, vol. SC-17, no. 1, pp. 28–33. Feb. 1982.
29. J. Ahrens and U. Dieter, “Sampling from binomial and Poisson distributions: A method with bounded computation times,” Computing, vol. 25, no. 31980, pp. 193–208.
30. D. Knuth, Seminumerical Algorithms (vol. 2, The Art of Computer Programming). Reading, MA: Addison-Wesley, 1981.
31. J. Ahrens and U. Dieter, “Computer methods for sampling from gamma, beta, Poisson and binomial distributions,” Computing, vol. 12, no. 31974, pp. 223–246.
32. W. Maly, A. Strojwas, and S. Director, “VLSI yield prediction and estimation: A unified framework,” IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, pp. 114–130, Jan. 1986.