ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 7, 2006, Pages 754-761

  Biswas, Partha ^a,b   Banerjee, Sudarshan ^a,c   Dutt, Nikil D ^a,c   Pozzi, Laura ^a,d   Ienne, Paolo ^a,e  

^a IEEE   (United States)

^b MATHWORKS INC   (United States)

^c University of California   (United States)

^d UNIVERSITY OF LUGANO   (Switzerland)

^e EPFL   (Switzerland)

Author keywords

Application specific processors; Hardware software partitioning; Instruction set extensions

Indexed keywords

APPLICATION-SPECIFIC PROCESSORS; EXPERIENCED DESIGNERS; HARDWARE-SOFTWARE PARTITIONING; INSTRUCTION SET EXTENSIONS;

CRYPTOGRAPHY; EMBEDDED SYSTEMS; ITERATIVE METHODS; LARGE SCALE SYSTEMS; PROGRAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 33746904375     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878345     Document Type: Conference Paper

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