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Volumn 2005, Issue , 2005, Pages 630-635

Performance improvements using coarse-grain reconfigurable logic in embedded SOCS

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE;

EID: 33746880687     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515801     Document Type: Conference Paper
Times cited : (7)

References (17)
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    • Improving software performance with configurable logic
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    • Villareal, J.1
  • 4
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    • Energy savings and speedups from partitioning critical software loops to hardware in embedded systems
    • Feb.
    • G. Stitt et al., "Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems", in ACM Trans. on Embedded Computing Systems (TECS), vol.3, no.1, pp. 218-232, Feb. 2004.
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    • Stitt, G.1
  • 5
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    • A decade of reconfigurable computing: A visionary retrospective
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    • Hartenstein, R.1
  • 6
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    • Mapping wireless communication algorithms onto a reconfigurable architecture
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    • G. K. Rauwerda et al., "Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture", in the Journal of Supercomputing, vol. 30, no. 3, pp. 263-282, Dec. 2004.
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    • Rauwerda, G.K.1
  • 7
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    • Instruction generation and regularity extraction for reconfigurable processors
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.