A portable clock multiplier generator using digital CMOS standard cells

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 958-965

  Combes, Michel ^a,b,c,d   Dioury, Karim ^a,d   Greiner, Alain ^a,d,e,f,g,h  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

^b TEXAS INSTRUMENTS   (France)

^c Institute Supérieur d'Electronique de Paris   (France)

^d SORBONNE UNIVERSITÉ   (France)

^e UNIVERSITÉ PARIS DESCARTES   (France)

^f Commsrt À l'Energie Atomique ^*

^g BULL Company

^h MASI Laboratory

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL CIRCUITS; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT MANUFACTURE; MICROCOMPUTERS; PHASE LOCKED LOOPS; SIGNAL GENERATORS; TIMING CIRCUITS; VLSI CIRCUITS;

DIGITAL CMOS STANDARD CELLS; DIGITAL DELAY LOCKED LOOP; PORTABLE CLOCK MULTIPLIER GENERATOR; SYNCHRONOUS DATA FLOW EXCHANGE;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 0030192894     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508209     Document Type: Article

References (13)

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