1.0-nsec 32-bit prefix tree adder in 0.25-μm static CMOS

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages 608-612

  Goldovsky, A ^a   Kolagotla, R K ^a   Nicol, C J ^a   Besz, M ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MATHEMATICAL OPERATORS; TREES (MATHEMATICS);

DYNAMIC CIRCUIT; PREFIX TREE ADDER; STATIC CIRCUIT;

ADDERS;

EID: 0033292813     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)