Capacitorless IT DRAM sensing scheme with automatic reference generation

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 6, 2006, Pages 1463-1469

  Blagojevic, Marija ^a,b   Kayal, Maher ^b   Pastre, Marc ^b   Harik, Louis ^a,b   Declercq, Michel J ^a,b   Okhonin, Serguei ^b   Fazan, Pierre C ^a,b  

^a IEEE   (Switzerland)

^b EPFL   (Switzerland)

Author keywords

Adjustable current source; Capacitorless 1 transistor DRAM; Floating body effect; Partially depleted silicon on insulator; Successive approximations algorithm

Indexed keywords

ADJUSTABLE CURRENT SOURCE; CAPACITORLESS 1-TRANSISTOR; FLOATING BODY EFFECT; PARTIALLY DEPLETED SILICON-ON-INSULATOR; SUCCESSIVE APPROXIMATIONS;

ALGORITHMS; AUTOMATION; CAPACITORS; ELECTRIC CURRENT DISTRIBUTION MEASUREMENT; ELECTRIC PROPERTIES; SILICON ON INSULATOR TECHNOLOGY; SOLID STATE DEVICE STRUCTURES; TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33746589171     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874357     Document Type: Article

References (20)

1. B. Keeth and R. J. Baker, DRAM Circuit Design. New York: IEEE Press, 2001.
2. R. H. Dennard, "Field effect transistor memory," U.S. patent 3, 387, 286, Jun. 4, 1968.
3. S. S. lyer and H. L. Kalter, "Embedded DRAM technology: opportunities and challenges," IEEE Spectrum, vol. 36, no. 4, pp. 56-64, Apr. 1999.
4. S. Okhonin, M. Nagoga, J. M. Sallese, and P. C. Fazan, "A SOI capacitorless IT-DRAM concept," in Proc. IEEE Int. SOI Conf., Oct. 2001, pp. 153-154.
5. P. C. Fazan, S. Okhonin, M. Nagoga, and J. M. Sallese, "A simple 1-transistor capacitorless memory cell for high performance embedded DRAMs," in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp. 99-102.
6. P. C. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borshchberg, and M. Declercq, "Capacitorless 1-transistor DRAM," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 10-13.
7. T. Ohsawa, K. Fujita, T. Higashi. Y. Ywata, T. Kajiyama, Y. Asao, and K. Sunouchi, "Memory design using a one-transistor gain cell on SOI," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1510-1522, Nov. 2002.
8. R. Ranica, A. Villaret, P. Maligne, P. Mazoyer, D. Lenoble, and P. Candelier et al., "A one transistor cell on bulk substrate (IT-bulk) for low-cost and high density eDRAM," in Symp. VLSI Technology Dig. Tech. Papers, 2004, pp. 128-129.
9. R. Ranica, A. Villaret, C. Fenouillet-Beranger, P. Malinge, P. Mazoyer, and P. Massen et al., "A capacitorless DRAM cell on 75 nm gate lenght, 16 nm thin fully depleted SOI device for high density embedded memories," in IEEE IEDM Tech. Dig., 2004, pp. 277-280.
10. T. Tanaka, E. Yoshida, and T. Miyashita, "Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM," in IEEE IEDM Tech. Dig., 2004, pp. 919-922.
11. M. Blagojevic, M. Pastre, M. Kayal, P. Fazan, S. Okhonin, M. Nagoga, and M. Declercq. "SOI capacitorless 1-transistor DRAM sensing scheme with automatic reference generation," in Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp. 182-183.
12. L. Portmann, M. Kayal, M. Pastre, M. Blagojevic, and M. Declercq. " Reference current generator, and method of programming, adjusting and/or operating same," U.S. patent 6, 912, 150, Jun. 28, 2005.
13. T. N. Blalock and R. C. Jaeger. "A high-speed sensing scheme for IT dynamic RAMs utilizing the clamped bit-line sense amplifier," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 618-625, Apr. 1992.
14. _. "A high-speed clamped bit-line current-mode sense amplifier," IEEE J. Solid-State. Circuits, vol. 26, no. 4, pp. 542-548, Apr. 1991.
15. M. Kayal, R. T. L. Saez, and M. Declercq, "An automatic offset compensation technique applicable to existing operational amplifier core cell," in Proc. IEEE Custom Integrated Circuits Conf., May 1998, pp. 419-422.
16. Z. B. Randjelovic, M. Kayal, R. Popovic, and H. Blanchard, "Highly sensitive hall magnetic sensor microsystem in CMOS technology," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 151-159, Feb. 2002.
17. K. Bult and G. J. Geelen, "An inherently linear and compact MOSTonly current division technique," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1730-1735, Dec. 1992.
18. E. Vittoz and X. Arreguit, "Linear networks based on transistors," IEEE Electron. Lett., vol. 29, no. 2, pp. 297-299, Feb. 1993.
19. M. Pastre, "Methodology for the digital calibration of analog circuits and systems-Application to a Hall sensor microsystem," Ph.D. dissertation, no. 3210, Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland, 2005.
20. T. Tanaka, E. Yoshida, and T. Miyashita, "Scalability study on a capacitorless IT-DRAM: from single-gate PD-SOI to double-gate FinDRAM," in IEEE Int. Electron Devices Meeting (IEDM) Dig. Papers, 2004, pp. 919-922.