SOI capacitor-less 1-transistor DRAM sensing scheme with automatic reference generation

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 182-183

  Blagojevic, M ^a   Pastre, M ^a   Kayal, M ^a   Fazan, P ^a,b   Okhonin, S ^a,b   Nagoga, M ^a,b   Declercq, M ^a  

^a EPFL   (Switzerland)

^b Innovative Silicon SA   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AMPLIFIERS (ELECTRONIC); APPROXIMATION THEORY; BUFFER CIRCUITS; CAPACITORS; COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; SILICON ON INSULATOR TECHNOLOGY; STATISTICAL METHODS;

APPROXIMATION ALGORITHMS; CLAMPED BIT-LINE SENSE AMPLIFIER (CBLSA); FLOATING BODY (FB) EFFECTS; MEMORY CELL (MC);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 4544291997     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. P. C. Fazan et al., "Capacitor-less 1-Transistor DRAM," in Proc. IEEE SOI Conf., pp.10-13, Oct. 2002.
2. S.Okhonin et al, "A SOI Capacitor-less IT- DRAM Concept," in Proc. IEEE. SOI Conf., pp. 153-154, Oct. 2001.
3. Takashi et al., "Memory Design Using a One-Transistor Gain Cell on SOI," IEEE JSSC, vol. 37, pp. 1510-1522, Nov. 2002.
4. T. N. Blalock et al., "A high-speed sensing scheme for IT dynamic RAMs utilizing the clamped bit-line sense amplifier," IEEE JSSC, vol. 27, pp. 618-625, Apr. 1992.