Memory design using a one-transistor gain cell on SOI

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1510-1522

  Ohsawa, Takashi ^a   Fujita, Katsuyuki ^a   Higashi, Tomoki ^a   Iwata, Yoshihisa ^a   Kajiyama, Takeshi ^a   Asao, Yoshiyuki ^a   Sunouchi, Kazumasa ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Capacitor less DRAM; DRAM; Embedded memory; Floating body transistor cell; Gain cell; Nondestructive readout; Silicon on insulator technology

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CHARGE; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; NONDESTRUCTIVE READOUT; SILICON ON INSULATOR TECHNOLOGY;

ARRAY DRIVING METHOD; CELL SIGNAL SENSING SYSTEM; FLOATING BODY TRANSISTOR CELL; ONE TRANSISTOR GAIN CELL; SELF ALIGNED CONTACT TECHNOLOGIES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036857083     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.802359     Document Type: Article

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