Scalable architecture for SoC video encoders

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 44, Issue 1-2, 2006, Pages 79-95

  Kangas, Tero ^a   Hämäläinen, Timo D ^a   Kuusilinna, Kimmo ^b  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

Architecture exploration; System on chip; Video encoding

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

ARCHITECTURE EXPLORATION; SINGLE PROGRAM MULTIPLE DATA (SPMD); SYSTEM-ON-CHIP; VIDEO ENCODING;

IMAGE CODING;

EID: 33746469059     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11265-006-5918-x     Document Type: Article

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