Parameter optimization tool for enhancing on-chip network performance

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Riihimäki, Jouni ^a   Salminen, Erno ^a   Kuusilinna, Kimmo ^a   Hämälänen, Timo ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; DATA COMMUNICATION SYSTEMS; DATA TRANSFER; INTERCONNECTION NETWORKS; ITERATIVE METHODS; OPTIMIZATION; RESOURCE ALLOCATION;

NETWORK-ON-A-CHIP; SYSTEM-ON-CHIP DEVICES;

SYSTEMS ANALYSIS;

EID: 0036287232     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Addressing the system-on-a-chip interconnect woes through communication-based design
2. Efficient exploration of the SoC communication architecture design space
3. Analytical optimization using computer algebraic manipulation
4. An analytical paradigm to compare routing strategies in an ATM multimedia environment
5. Early evaluation of bus interconnects dependability for system-on-chip designs
6. Low latency interconnection for IP-block based multimedia chips