Area-efficient register organization for fully-synthesizable VLIW DSP cores

International Journal of Electrical Engineering

Volumn 13, Issue 2, 2006, Pages 117-127

  Lin, Tay Jyi ^a   Liu, Chih Wei ^a   Hsiao, Pi Chen ^b   Jen, Chein Wei ^a,b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

And digital signal processor (DSP); Banking; Clustering; Register file; Very long instruction word (VLIW)

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; FILE ORGANIZATION; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT;

BANKING; DIGITAL SIGNAL PROCESSOR (DSP); REGISTER FILE; VERY LONG INSTRUCTION WORD (VLIW);

DIGITAL SIGNAL PROCESSING;

EID: 33746383469     PISSN: 18123031     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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