A unified processor architecture for RISC & VLIW DSP

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 50-55

  Lin, Tay Jyi ^a   Chao, Chie Min ^a   Liu, Chia Hsien ^a   Hsiao, Pi Chen ^a   Chen, Shin Kai ^a   Lin, Li Chun ^a   Liu, Chih Wei ^a   Jen, Chein Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Digital signal processor; Dual core processor; Register organization; Variable length instruction encoding

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; VLSI CIRCUITS;

DIGITAL SIGNAL PROCESSOR; DUAL-CORE PROCESSOR; REGISTER ORGANIZATION; VARIABLE-LENGTH INSTRUCTION ENCODING;

REDUCED INSTRUCTION SET COMPUTING;

EID: 29244486806     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057675     Document Type: Conference Paper

References (24)

1. Intel PXA800F Cellular Processor - Development Manual, Intel Corp., Feb. 2003
2. OMAP5910 Dual Core Processor - Technical Reference Manual, Texas Instruments, Jan. 2003
3. M. Levy, "ARM picks up performance," Microprocessor Report, 4/7/03-01
4. R. A. Quinnell, "Logical combination? Convergence products need both RISC and DSP processors, but merging them may not be the answer," EDN, 1/23/2003
5. J. L Hennessy, and D. A. Patterson, Computer Architecture - A Quantitative Approach, 3rd Edition, Morgan Kaufmann, 2002
6. S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, "Register organization for media processing," in Proc. HPCA-6, 2000, pp.375-386
7. J. Zalamea, J. Llosa, E. Ayguade, and M. Valero, "Hierarchical clustered register file organization for VLIW processors," in Proc. IPDPS, 2003, pp.77-86
8. P. Faraboschi, G. Brown, J. A. Fisher, G. Desoll, and F. M. O. Homewood, "Lx: a technology platform for customizable VLIW embedded processing," in Proc. ISCA, 2000, pp.203-213
9. E. F. Barry, G. G. Pechanek, and P. R. Marchand, "Register file indexing methods and apparatus for providing indirect control of register file addressing in a VLIW processor," International Application Published under the Patent Cooperation Treaty (PCT), WO 00/54144, Mar. 9 2000
10. TMS320C64x DSP Library Programmer's Reference, Texas Instruments Inc., Apr 2002
11. K. Arora, H. Sharangpani, and R. Gupta, "Copied register files for data processors having many execution units" U.S. Patent 6,629,232, Sep. 30, 2003
12. A. Kowalczyk et al., "The first MAJC microprocessor: a dual CPU system-on-a-chip," IEEE J. Solid-State Circuits, vol. 36, pp.1609-1616, Nov. 2001
13. A. Terechko, E. L. Thenaff, M. Garg, J. Eijndhoven, and H. Corporaal, "Inter-cluster communication models for clustered VLIW processors," in Proc. HPCA-9, 2003, pp.354-364
14. H. Pan and K. Asanovic, "Heads and tails: a variable-length instruction format supporting parallel fetch and decode," in Proc. CASES, 2001
15. G. G. Pechanek and S. Vassiliadis, "The ManArray embedded processor architecture," Euromicro Conf., vol.1, pp.348-355, Sep., 2000
16. G. Fettweis, M. Bolle, J. Kneip, and M. Weiss, "OnDSP: a new architecture for wireless LAN applications," Embedded Processor Forum, May 2002
17. TMS320C55x DSP Programmer's Guide, Texas Instruments Inc., July 2000
18. T. Kumura, M. Ikekawa, M. Yoshida, and I. Kuroda, "VLIW DSP for mobile applications," IEEE Signal Processing Mag., pp. 10-21, July 2002
19. R. K. Kolagotla, et al, "A 333-MHz dual-MAC DSP architecture for next-generation wireless applications," in Proc. ICASSP, 2001, pp.l013-1016
20. W. B. Pennebaker and J. L. Mitchell, JPEG - Still Image Data Compression Standard, Van Nostrand Reinhold, 1993
21. T. J. Lin, C. C. Chang, C. C. Lee, and C. W. Jen, "An efficient VLIW DSP architecture for baseband processing," in Proc. ICCD, 2003
22. P. Lapsley, J. Bier, A. Shoham, and E. A. Lee, DSP Processor Fundamentals - Architectures and Features, IEEE Press, 1996
23. TriCore 2-32-bit Unified Processor Core v.2.0 Architecture - Architecture Manual, Infineon Technology, June 2003
24. Y. H. Hu, Programmable Digital Signal Processors - Architecture. Programming, and Applications, Marcel Dekker Inc., 2002