-
1
-
-
0034581535
-
Register organization for media processing
-
S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, "Register organization for media processing," in Proc. HPCA-6, 2000, pp.375-386
-
(2000)
Proc. HPCA-6
, pp. 375-386
-
-
Rixner, S.1
Dally, W.J.2
Khailany, B.3
Mattson, P.4
Kapasi, U.J.5
Owens, J.D.6
-
2
-
-
0038008204
-
Banked multiported register files for high-frequency superscalar microprocessors
-
J. H. Tseng and K. Asanovic, "Banked multiported register files for high-frequency superscalar microprocessors," in Proc. ISCA, 2003, pp.62-71
-
(2003)
Proc. ISCA
, pp. 62-71
-
-
Tseng, J.H.1
Asanovic, K.2
-
3
-
-
0032639289
-
The Alpha 21264 microprocessor
-
Mar.-Apr.
-
R. E. Kessler, "The Alpha 21264 microprocessor," IEEE Micro, vol.19, pp.24-36, Mar.-Apr.1999
-
(1999)
IEEE Micro
, vol.19
, pp. 24-36
-
-
Kessler, R.E.1
-
4
-
-
84955466213
-
Inter-cluster communication models for clustered VLIW processors
-
A. Terechko, E. L. Thenaff, M. Garg, J. Eijndhoven, and H. Corporaal, "Inter-cluster communication models for clustered VLIW processors," in Proc. HPCA-9, 2003, pp.354-364
-
(2003)
Proc. HPCA-9
, pp. 354-364
-
-
Terechko, A.1
Thenaff, E.L.2
Garg, M.3
Eijndhoven, J.4
Corporaal, H.5
-
5
-
-
84947286374
-
Hierarchical clustered register file organization for VLIW processors
-
J. Zalamea, J. Llosa, E. Ayguade, and M. Valero, "Hierarchical clustered register file organization for VLIW processors," in Proc. IPDPS, 2003, pp.77-86
-
(2003)
Proc. IPDPS
, pp. 77-86
-
-
Zalamea, J.1
Llosa, J.2
Ayguade, E.3
Valero, M.4
-
6
-
-
0033703885
-
Lx: A technology platform for customizable VLIW embedded processing
-
P. Faraboschi, G. Brown, J. A. Fisher, G. Desoll, and F. M. O. Homewood, "Lx: a technology platform for customizable VLIW embedded processing," in Proc. ISCA, 2000, pp.203-213
-
(2000)
Proc. ISCA
, pp. 203-213
-
-
Faraboschi, P.1
Brown, G.2
Fisher, J.A.3
Desoll, G.4
Homewood, F.M.O.5
-
7
-
-
33745476769
-
Register file indexing methods and apparatus for providing indirect control of register file addressing in a VLIW processor
-
WO 00/54144, Mar. 9
-
E. F. Barry, G. G. Pechanek, and P. R. Marchand, "Register file indexing methods and apparatus for providing indirect control of register file addressing in a VLIW processor," International Application Published under the Patent Cooperation Treaty (PCT), WO 00/54144, Mar. 9 2000
-
(2000)
International Application Published under the Patent Cooperation Treaty (PCT)
-
-
Barry, E.F.1
Pechanek, G.G.2
Marchand, P.R.3
-
9
-
-
33745459599
-
-
"Copied register files for data processors having many execution units" U.S. Patent 6 629 232, Sep. 30
-
K. Arora, H. Sharangpani, and R. Gupta, "Copied register files for data processors having many execution units" U.S. Patent 6 629 232, Sep. 30, 2003
-
(2003)
-
-
Arora, K.1
Sharangpani, H.2
Gupta, R.3
-
10
-
-
6644227176
-
The first MAJC microprocessor: A dual CPU system-on-a-chip
-
Nov.
-
A. Kowalczyk et al., "The first MAJC microprocessor: a dual CPU system-on-a-chip," IEEE J. Solid-State Circuits, vol. 36, pp.1609-1616, Nov. 2001
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, pp. 1609-1616
-
-
Kowalczyk, A.1
-
11
-
-
33745473627
-
Performance evaluation of ring-structure register file in multimedia applications
-
T. J. Lin, et al., "Performance evaluation of ring-structure register file in multimedia applications," in Proc. ICME, 2003, pp.121-124
-
(2003)
Proc. ICME
, pp. 121-124
-
-
Lin, T.J.1
-
13
-
-
85032751514
-
VLIW DSP for mobile applications
-
July
-
T. Kumura, M. Ikekawa, M. Yoshida, and I. Kuroda, "VLIW DSP for mobile applications," IEEE Signal Processing Mag., pp.10-21, July 2002
-
(2002)
IEEE Signal Processing Mag.
, pp. 10-21
-
-
Kumura, T.1
Ikekawa, M.2
Yoshida, M.3
Kuroda, I.4
-
14
-
-
85032751343
-
High-performance dual-MAC DSP architecture
-
July
-
R. K. Kolagotla, et al, "High-performance dual-MAC DSP architecture," IEEE Signal Processing Mag., pp.42-53, July 2002
-
(2002)
IEEE Signal Processing Mag.
, pp. 42-53
-
-
Kolagotla, R.K.1
-
15
-
-
0026984988
-
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors
-
M. Franklin and G. S. Sohi, "Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors," in Proc. MICRO-25, 1992, pp.23 6-245
-
(1992)
Proc. MICRO-25
, pp. 236-245
-
-
Franklin, M.1
Sohi, G.S.2
-
16
-
-
41349090027
-
Reducing register ports for higher speed and lower energy
-
I. Park, M. D. Powell, and T. N. Vijaykumar, "Reducing register ports for higher speed and lower energy," in Proc. MICRO-35, 2002, pp.171-182
-
(2002)
Proc. MICRO-35
, pp. 171-182
-
-
Park, I.1
Powell, M.D.2
Vijaykumar, T.N.3
-
17
-
-
0031624293
-
The energy complexity of register files
-
V. Zyuban and P. Kogge, "The energy complexity of register files," in Proc. ISLPED, 1998, pp.305-310
-
(1998)
Proc. ISLPED
, pp. 305-310
-
-
Zyuban, V.1
Kogge, P.2
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