Reversed Nested Miller Compensation with Voltage Buffer and Nulling Resistor

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 10, 2003, Pages 1735-1738

  Ho, Kin Pui ^a   Chan, Cheong Fat ^a   Choy, Chiu Sing ^a   Pun, Kong Pang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ENERGY UTILIZATION; FREQUENCY DOMAIN ANALYSIS; OPERATIONAL AMPLIFIERS; RESISTORS;

VOLTAGE BUFFER;

CMOS INTEGRATED CIRCUITS;

EID: 0141885999     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.817598     Document Type: Article

References (9)

1. G. Palmisano and G. Palumbo, "Analysis and compensation of two-pole amplifier with a pole-zero doublet," IEEE Trans. Circuits Syst. 1, vol. 46, pp. 846-868, July 1999.
2. K. N. Leung and P. K. T. Mok, "Nested Miller compensation in low-power CMOS design," IEEE Trans. Circuits Systems II, vol. 48, pp. 388-394, Apr. 2001.
3. G. Palumbo and S. Pennisi, "Design methodology and advances in nested Miller compensation," IEEE Trans. Circuits Syst. I, vol. 49, pp. 893-903, July 2002.
4. G. Di Cataldo, R. Mita, G. Palumbo, and S. Pennisi, "Reversed nested Miller compensation with voltage follower," in Proc. IEEE Int. Symp. Circuits and Systems, Phoenix, AZ, May 2002, pp. II827-II830.
5. R. Mita, G. Palumbo, and S. Pennisi, "Reversed nested Miller compensation with current follower," in Proc. IEEE Int. Symp. Circuits and Systems, May 2001, pp. 308-311.
6. _, "Hybrid nested Miller compensation with nulling resistors," in Proc. 9th Int. Conf. Electronics, Circuits, and Systems, vol. 1, 2002, pp. 177-180.
7. G. Palumbo and S. Pennisi, "Design methodology and advances in nested Miller compensation," IEEE Trans. Circuits Syst. I, vol. 49, pp. 893-903, July 2002.
8. K. Ramamurthy, J. Kenny, and G. Rangan, "On-chip tests for gain bandwidth product and slew rate," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, May 1993, pp. 1341-1344.
9. R. Mita, G. Palumbo, and S. Pennisi, "Reversed nested Miller compensation with current follower," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, 2001, pp. 308-311.