Design guidelines for reversed nested Miller compensation in three-stage amplifiers

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 5, 2003, Pages 227-233

  Mita, Rosario ^a   Palumbo, Gaetano ^a   Pennisi, Salvatore ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

Analog circuits; CMOS; Frequency compensation; Nested Miller; OTA

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC FREQUENCY CONTROL; ELECTRIC POTENTIAL; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; RESISTORS; TRANSCONDUCTANCE;

ANALOG CIRCUITS; REVERSED NESTED MILLER COMPENSATION; THREE STAGE AMPLIFIERS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037608791     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.811437     Document Type: Article

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