Verification of concurrent systems with parametric delays using octahedra

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 2005, Issue , 2005, Pages 122-131

  Clarisó, Robert ^a   Cortadella, Jordi ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER CIRCUITS; MICROPROCESSOR CHIPS; SECURITY SYSTEMS; SYSTEMS ENGINEERING;

CONVEX POLYHEDRA; OCTAHEDRAL; PARAMETRIC APPROACH;

CONCURRENT ENGINEERING;

EID: 33746265868     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2005.34     Document Type: Conference Paper

References (24)

1. R. Alur, C. Courcoubetis, N. Halbwachs, T. Henzinger, P.-H. Ho, X. Nicollin, A. Olivero, J. Sifakis, and S. Yovine. The algorithmic analysis of hybrid systems. Theoretical Computer Science, pages 3-34, 1995.
2. R. Alur and D. L. Dill. A theory of timed automata. Theoretical Computer Science, 126(2): 183-235, 1994.
3. R. Alur, T. A. Henzinger, and M. Y. Vardi. Parametric real-time reasoning. In ACM Symposium on Theory of Computing, pages 592-601, 1993.
4. T. Amon, G. Borriello, T. Hu, and J. Liu. Symbolic timing verification of timing diagrams using Presburger formulas. In Proc. Design Automation Conf., pages 226-231, 1997.
5. A. Annichini, E. Asarin, and A. Bouajjani. Symbolic techniques for parametric reasoning about counter and clock systems. In Computer Aided Verification, pages 419-434, 2000.
6. W. J. Belluomini and C. J. Myers. Timed circuit verification using TEL structures. IEEE Transactions on Computers, 20(1):129-146, 2001.
7. S. Chakraborty, D. L. Dill, and K. Y. Yun. Min-max timing analysis and an application to asynchronous circuits. Proceedings of the IEEE, 87(2):332-346, 1999.
8. T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. PhD thesis, MIT, June 1987.
9. R. Clarisó and J. Cortadella. The octahedron abstract domain. In Proc. Static Analysis Symp., pages 312-327, 2004.
10. R. Clarisó and J. Cortadella. Verification of timed circuits with symbolic delays. In Proc. of Asia and South Pacific Design Automation Conf., pages 628-633, 2004.
11. P. Cousot and R. Cousot. Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints. In Proc. Symp. on Principles of Programming Languages, pages 238-252, 1977.
12. P. Cousot and N. Halbwachs. Automatic discovery of linear restraints among variables of a program. In Proc. Symp. on Principles of Programming Languages, pages 84-97, 1978.
13. G. Dantzig and B. Eaves. Fourier-motzkin elimination and its dual. Journal of combinatorial theory, 14:288-297, 1973.
14. D. L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Automatic Verification Methods for Finite State Systems, LNCS 407, pages 197-212. Springer-Verlag, 1989.
15. N. Halbwachs, Y.-E. Proy, and P. Roumanoff. Verification of real-time systems using linear relation analysis. Formal Methods in System Design, 11(2):157-185, 1997.
16. T. A. Henzinger, Z. Manna, and A. Pnueli. Timed transition systems. In Proc. REX Workshop Real-Time: Theory in Practice, volume 600 of LNCS, pages 226-251, 1992.
17. A. Miné. The octagon abstract domain. In Analysis, Slicing and Tranformation (in Working Conference on Reverse Engineering), IEEE, pages 310-319. IEEE CS Press, 2001.
18. C. J. Myers, W. Belluomini, K. Killpack, E. Mercer, E. Peskin, and H. Zheng. Timed circuits: A new paradigm for high-speed design. In Proc. of Asia and South Pacific Design Automation Conference, pages 335-340, 2001.
19. M. A. Peña, J. Cortadella, A. Kondratyev, and E. Pastor. Formal verification of safety properties in timed circuits. In Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, pages 2-11, 2000.
20. S. Schuster, W. Reohr, P. Cook, D. Heidel, M. I. ato, and K. Jenkins. Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3 - 4.5GHz. In IEEE Int. Solid-State Circuits Conf. (ISSCC), pages 292-293, Feb. 2000.
21. K. Stevens, R. Ginosar, and S. Rotem. Relative timing. In Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, pages 208-218, 1999.
22. I. Sutherland and S. Fairbanks. GasP: A minimal FIFO control. In Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, pages 46-53, 2001.
23. F. Wang. Symbolic parametric safety analysis of linear hybrid systems with BDD-like data-structures. In Computer Aided Verification, July 2004.
24. T. Yoneda, T. Kitai, and C. Myers. Automatic derivation of timing constraints by failure analysis. In Proc. Int. Conference on Computer Aided Verification, pages 195-208, 2002.