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Volumn 2005, Issue , 2005, Pages 188-189

Formal methods for networks on chips

Author keywords

[No Author keywords available]

Indexed keywords


EID: 33746238141     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2005.36     Document Type: Conference Paper
Times cited : (9)

References (22)
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  • 4
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    • O. P. Gangwal et al. Building predictable systems on chip: An analysis of guaranteed communication in the Æthereal network on chip. In P. van der Stok, editor, Dynamic and Robust Streaming In And Between Connected Consumer-Electronics Devices. Kluwer, 2005.
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    • Gangwal, O.P.1
  • 6
    • 27344448207 scopus 로고    scopus 로고
    • A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification
    • K. Goossens et al. A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In DATE, 2005.
    • (2005) DATE
    • Goossens, K.1
  • 7
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  • 10
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.