-
1
-
-
33751398970
-
Post-verification debugging of hierarchical designs
-
M.F. Ali, S. Safarpour, A. Veneris, M.S. Abadir, and R. Drechsler. Post-verification debugging of hierarchical designs. In Int'l Conf. on CAD, pages 871-876, 2005.
-
(2005)
Int'l Conf. on CAD
, pp. 871-876
-
-
Ali, M.F.1
Safarpour, S.2
Veneris, A.3
Abadir, M.S.4
Drechsler, R.5
-
2
-
-
84944319371
-
Symbolic model checking without BDDs
-
Tools and Algorithms for the Construction and Analysis of Systems. Springer Verlag
-
A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Tools and Algorithms for the Construction and Analysis of Systems, volume 1579 of LNCS, pages 193-207. Springer Verlag, 1999.
-
(1999)
LNCS
, vol.1579
, pp. 193-207
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.3
Zhu, Y.4
-
3
-
-
84941162970
-
-
Boolean Satisfiability Research Group at Princeton University. ZCHAFF, 2004. http://www.princeton.edu/~chaff/zchaff.html.
-
(2004)
ZCHAFF
-
-
-
4
-
-
0020832565
-
Redundancy and don't cares in logic synthesis
-
D. Brand. Redundancy and don't cares in logic synthesis. IEEE Trans. on Comp., 32(10):947-952, 1983.
-
(1983)
IEEE Trans. on Comp.
, vol.32
, Issue.10
, pp. 947-952
-
-
Brand, D.1
-
6
-
-
85059770931
-
The complexity of theorem proving procedures
-
S.A. Cook. The complexity of theorem proving procedures. In 3. ACM Symposium on Theory of Computing, pages 151-158, 1971.
-
(1971)
3. ACM Symposium on Theory of Computing
, pp. 151-158
-
-
Cook, S.A.1
-
8
-
-
84881072062
-
A computing procedure for quantification theory
-
M. Davis and H. Putnam. A computing procedure for quantification theory. Journal of the ACM, 7:506-521, 1960.
-
(1960)
Journal of the ACM
, vol.7
, pp. 506-521
-
-
Davis, M.1
Putnam, H.2
-
11
-
-
26444549375
-
Effective preprocessing in SAT through variable and clause elimination
-
SAT 2005. Springer
-
N. Eén and A. Biere. Effective preprocessing in SAT through variable and clause elimination. In SAT 2005, volume 3569 of LNCS. Springer, 2005.
-
(2005)
LNCS
, vol.3569
-
-
Eén, N.1
Biere, A.2
-
12
-
-
30344450270
-
An extensible SAT solver
-
SAT 2003
-
N. Eén and N. Sörensson. An extensible SAT solver. In SAT 2003, volume 2919 of LNCS, pages 502-518, 2004.
-
(2004)
LNCS
, vol.2919
, pp. 502-518
-
-
Eén, N.1
Sörensson, N.2
-
14
-
-
34047178467
-
On the relation between simulation-based and SAT-based diagnosis
-
G. Fey, S. Safarpour, A. Veneris, and R. Drechsler. On the relation between simulation-based and SAT-based diagnosis. In Design, Automation and Test in Europe, 2006.
-
(2006)
Design, Automation and Test in Europe
-
-
Fey, G.1
Safarpour, S.2
Veneris, A.3
Drechsler, R.4
-
16
-
-
0015757537
-
Easily testable iterative systems
-
A.D. Friedman. Easily testable iterative systems. In IEEE Trans. on Comp., volume 22, pages 1061-1064, 1973.
-
(1973)
IEEE Trans. on Comp.
, vol.22
, pp. 1061-1064
-
-
Friedman, A.D.1
-
17
-
-
0020923381
-
On the acceleration of test generation algorithms
-
H. Fujiwara and T. Shimono. On the acceleration of test generation algorithms. IEEE Trans. on Comp., 32:1137-1144, 1983.
-
(1983)
IEEE Trans. on Comp.
, vol.32
, pp. 1137-1144
-
-
Fujiwara, H.1
Shimono, T.2
-
18
-
-
0019543877
-
An implicit enumeration algorithm to generate tests for combinational logic
-
P. Goel. An implicit enumeration algorithm to generate tests for combinational logic. IEEE Trans. on Comp., 30:215-222, 1981.
-
(1981)
IEEE Trans. on Comp.
, vol.30
, pp. 215-222
-
-
Goel, P.1
-
20
-
-
0017430454
-
Delay test generation
-
E. R. Hsieh, R. A. Rasmussen, L. J. Vidunas, and W. T. Davis. Delay test generation. In Design Automation Conf., pages 486-491, 1977.
-
(1977)
Design Automation Conf.
, pp. 486-491
-
-
Hsieh, E.R.1
Rasmussen, R.A.2
Vidunas, L.J.3
Davis, W.T.4
-
22
-
-
26444549823
-
CirCUs: A hybrid satisfiability solver
-
SAT 2004. Springer Verlag
-
H. Jin and F. Somenzi. CirCUs: A hybrid satisfiability solver. In SAT 2004, volume 3542 of LNCS, pages 211-223. Springer Verlag, 2005.
-
(2005)
LNCS
, vol.3542
, pp. 211-223
-
-
Jin, H.1
Somenzi, F.2
-
23
-
-
0018924690
-
Undetectability of bridging faults and validity of stuck-at fault test sets
-
K. L. Kodandapani and D. K. Pradhan. Undetectability of bridging faults and validity of stuck-at fault test sets. IEEE Trans. on Comp., C-29(1):55-59, 1980.
-
(1980)
IEEE Trans. on Comp.
, vol.C-29
, Issue.1
, pp. 55-59
-
-
Kodandapani, K.L.1
Pradhan, D.K.2
-
24
-
-
0036918496
-
Robust Boolean reasoning for equivalence checking and functional property verification
-
A. Kuehlmann, V. Paruthi, F. Krohm, and M.K. Ganai. Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. on CAD, 21(12):1377-1394, 2002.
-
(2002)
IEEE Trans. on CAD
, vol.21
, Issue.12
, pp. 1377-1394
-
-
Kuehlmann, A.1
Paruthi, V.2
Krohm, F.3
Ganai, M.K.4
-
25
-
-
0027839536
-
HANNIBAL: An efficient tool for logic verification based on recursive learning
-
W. Kunz. HANNIBAL: An efficient tool for logic verification based on recursive learning. In Int'l Conf. on CAD, pages 538-543, 1993.
-
(1993)
Int'l Conf. on CAD
, pp. 538-543
-
-
Kunz, W.1
-
26
-
-
0028501364
-
Recursive learning: A new implication technique for efficient solutions of CAD problems: Test, verification and optimization
-
W. Kunz and D.K. Pradhan. Recursive learning: A new implication technique for efficient solutions of CAD problems: Test, verification and optimization. IEEE Trans. on CAD, 13(9):1143-1158, 1994.
-
(1994)
IEEE Trans. on CAD
, vol.13
, Issue.9
, pp. 1143-1158
-
-
Kunz, W.1
Pradhan, D.K.2
-
27
-
-
0026623575
-
Test pattern generation using Boolean satisfiability
-
T. Larrabee. Test pattern generation using Boolean satisfiability. IEEE Trans. on CAD, 11:4-15, 1992.
-
(1992)
IEEE Trans. on CAD
, vol.11
, pp. 4-15
-
-
Larrabee, T.1
-
28
-
-
0005665884
-
Atalanta: An efficient ATPG for combinational circuits
-
Dep. of Electrical Engineering, Virginia Polytechnic Institute and State University
-
H.K. Lee and D.S. Ha. Atalanta: An efficient ATPG for combinational circuits. Technical Report 12, Dep. of Electrical Engineering, Virginia Polytechnic Institute and State University, 1993.
-
(1993)
Technical Report
, vol.12
-
-
Lee, H.K.1
Ha, D.S.2
-
30
-
-
0005511569
-
Robust search algorithms for test pattern generation
-
Dept. of Informatics, Technical University of Lisbon, Lisbon, Protugal, January
-
J.P. Marques-Silva and K.A. Sakallah. Robust search algorithms for test pattern generation. Technical Report RT/02/97, Dept. of Informatics, Technical University of Lisbon, Lisbon, Protugal, January 1997.
-
(1997)
Technical Report
, vol.RT-02-97
-
-
Marques-Silva, J.P.1
Sakallah, K.A.2
-
31
-
-
0032680865
-
GRASP: A search algorithm for prepositional satisfiability
-
J.P. Marques-Silva and K.A. Sakallah. GRASP: A search algorithm for prepositional satisfiability. IEEE Trans. on Comp., 48(5):506-521, 1999.
-
(1999)
IEEE Trans. on Comp.
, vol.48
, Issue.5
, pp. 506-521
-
-
Marques-Silva, J.P.1
Sakallah, K.A.2
-
32
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conf., pages 530-535, 2001.
-
(2001)
Design Automation Conf.
, pp. 530-535
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
34
-
-
0001413253
-
Diagnosis of automata failures: A calculus and a method
-
J.P. Roth. Diagnosis of automata failures: A calculus and a method. IBM J. Res. Dev., 10:278-281, 1966.
-
(1966)
IBM J. Res. Dev.
, vol.10
, pp. 278-281
-
-
Roth, J.P.1
-
35
-
-
0023558527
-
SOCRATES: A highly efficient automatic test pattern generation system
-
M. Schulz, E. Trischler, and T. Sarfert. SOCRATES: A highly efficient automatic test pattern generation system. In Int'l Test Conf., pages 1016-1026, 1987.
-
(1987)
Int'l Test Conf.
, pp. 1016-1026
-
-
Schulz, M.1
Trischler, E.2
Sarfert, T.3
-
36
-
-
0003934798
-
SIS: A system for sequential circuit synthesis
-
University of Berkeley
-
E. Sentovich, K. Singh, L. Lavagno, Ch. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical report, University of Berkeley, 1992.
-
(1992)
Technical Report
-
-
Sentovich, E.1
Singh, K.2
Lavagno, L.3
Moon, Ch.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.8
Brayton, R.9
Sangiovanni-Vincentelli, A.10
-
37
-
-
26844504869
-
PASSAT: Effcient SAT-based test pattern generation for industrial circuits
-
J. Shi, G. Fey, R. Drechsler, A. Glowatz, F. Hapke, and J. Schlöffel. PASSAT: Effcient SAT-based test pattern generation for industrial circuits. In IEEE Annual Symposium on VLSI, pages 212-217, 2005.
-
(2005)
IEEE Annual Symposium on VLSI
, pp. 212-217
-
-
Shi, J.1
Fey, G.2
Drechsler, R.3
Glowatz, A.4
Hapke, F.5
Schlöffel, J.6
-
38
-
-
33751053759
-
Experimental studies on SAT-based test pattern generation for industrial circuits
-
J. Shi, G. Fey, R. Drechsler, A. Glowatz, J. Schlöffel, and F. Hapke. Experimental studies on SAT-based test pattern generation for industrial circuits. In Int'l Conf. on ASIC, pages 967-970, 2005.
-
(2005)
Int'l Conf. on ASIC
, pp. 967-970
-
-
Shi, J.1
Fey, G.2
Drechsler, R.3
Glowatz, A.4
Schlöffel, J.5
Hapke, F.6
-
40
-
-
0022307908
-
Model for delay faults based upon paths
-
G.L. Smith. Model for delay faults based upon paths. In Int'l Test Conf., pages 342-349, 1985.
-
(1985)
Int'l Test Conf.
, pp. 342-349
-
-
Smith, G.L.1
-
43
-
-
0033337596
-
SAT based ATPG using fast justification and propagation in the implication graph
-
P. Tafertshofer and A. Ganz. SAT based ATPG using fast justification and propagation in the implication graph. In Int'l Conf. on CAD, pages 139-146, 1999.
-
(1999)
Int'l Conf. on CAD
, pp. 139-146
-
-
Tafertshofer, P.1
Ganz, A.2
-
44
-
-
0031341194
-
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
-
P. Tafertshofer, A. Ganz, and M. Henftling. A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. In Int'l Conf. on CAD, pages 648-655, 1997.
-
(1997)
Int'l Conf. on CAD
, pp. 648-655
-
-
Tafertshofer, P.1
Ganz, A.2
Henftling, M.3
-
45
-
-
0015564343
-
Enhancing testability of large-scale integrated circuits via test points and additional logic
-
M. J. Y. Williams and J. B. Angell. Enhancing testability of large-scale integrated circuits via test points and additional logic. IEEE Trans. on Comp., C-22(1):46-60, 1973.
-
(1973)
IEEE Trans. on Comp.
, vol.C-22
, Issue.1
, pp. 46-60
-
-
Williams, M.J.Y.1
Angell, J.B.2
-
46
-
-
0035209012
-
Efficient conflict driven learning in a Boolean satisfiability solver
-
L. Zhang, C. F. Madigan, M. H. Moskewicz, and S. Malik. Efficient conflict driven learning in a Boolean satisfiability solver. In Int'l Conf. on CAD, pages 279-285, 2001.
-
(2001)
Int'l Conf. on CAD
, pp. 279-285
-
-
Zhang, L.1
Madigan, C.F.2
Moskewicz, M.H.3
Malik, S.4
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