Experimental studies on SAT-based test pattern generation for industrial circuits

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings

Volumn 2, Issue , 2005, Pages 967-970

  Shi, Junhao ^a   Fey, Görschwin ^a   Drechsler, Rolf ^a   Glowatz, Andreas ^b   Schlöffel, Jürgen ^b   Hapke, Friedrich ^b  

^a UNIVERSITY OF BREMEN   (Germany)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; HEURISTIC METHODS; INTEGRATED CIRCUIT MANUFACTURE; PROBLEM SOLVING;

BOOLEAN SATISFIABILITY; INDUSTRIAL CIRCUITS; TEST PATTERN GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 33751053759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. M. Davis, G. Logeman, D. Loveland: A machine program for theorem proving, Comm. of the ACM, Vol. 5, No. 7, pp. 394-397, 1962.
2. N. Eén, N. Sörensson: An extensible SAT solver. In. Proc. of SAT 2003, LNCS, Vol. 2919, pp. 502-518, 2004.
3. H. Fujiwara and T. Shimono. On the acceleration of test generation algorithms. IEEE Trans, on Computers, Vol. 32, No. 12, pp. 1137-1144, 1983.
4. E.Goldberg, Y.Novikov: BerkMin: A fast and robust SAT solver. In Proc. of DATE, pp. 142-149, 2002.
5. P. Goel. An implicit enumeration algorithm to generate test for combinational logic. IEEE Trans, on Computers, Vol. 30, No. 3, pp. 215-222, 1981.
6. D. S. Johnson, M. A. Trick, ed.: Appendix summarizing results of walksat on challenge instances, in DIMACS Series in Discrete Mathematics and Theoretical Computer Science, Vol. 26, AMS, 1996.
7. M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, S. Malik: Zchaff: Engineering an efficient SAT solver. In Proc. of Design Automation Conference, pp. 530-535, 2001.
8. J. P. Marques-Silva, K. A. Sakallah : GRASP: A search algorithm for prepositional satisfiability. In IEEE Trans, on Computers, Vol. 48, No. 5, pp. 506-521, 1999.
9. J. Roth. Diagnosis of automata failures: A calculus and a method. IBM J. Res. Dev., Vol. 10, pp. 278-281, 1966.
10. P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. Combinational test generation using satisfiability. IEEE Trans. on CAD, Vol. 15, No. 9, pp. 1167-1176, 1996.
11. J. Shi, G. Fey, R. Drechsler, A. Glowatz, J. Schlöffel, F. Hapke: PASSAT: Efficient SAT-based test pattern generation for industrial circuits. In Proc. of ISVLSI, pp. 212-217, 2005.