Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies

Microelectronics Journal

Volumn 37, Issue 9, 2006, Pages 851-860

  Ekekwe, Ndubuisi ^a   Etienne Cummings, Ralph ^a  

^a Whiting School of Engineering   (United States)

Author keywords

Control techniques; Leakage current; Power dissipation; Semiconductor roadmap; Submicron CMOS

Indexed keywords

CONSTRAINT THEORY; ENERGY DISSIPATION; LEAKAGE CURRENTS; OXIDES; PROBLEM SOLVING; SEMICONDUCTOR DEVICES;

CONTROL TECHNIQUES; LEAKAGE CURRENT; POWER DISSIPATION; SEMICONDUCTOR ROADMAP; SUBMICRON CMOS;

CMOS INTEGRATED CIRCUITS;

EID: 33745904460     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2006.03.008     Document Type: Article

References (24)

1. Y. Taur, E. Nowark, CMOS devices below 0.1 um: how high will performance go?, Electron Devices Meeting, Technical Digest., International Publication, 7-10 December 1997, pp. 215-218.
2. Sylvester D., and Kaul H. Power-driven challenges in nanometer design. IEEE Des. Test Comput. 13 (2001) 12-21
3. Uyemura J. Chip Design for Submicron VLSI: CMOS Layout and Simulation (2006), Toronto, Thomson
4. E. Sicard, CMOS Design, Online Courseware, available at http://www.microwind.org/.
5. Sicard E., and Bendhia D.S. Basics of CMOS Design (2005), Tata, McGraw-Hill, New Delhi
6. International Technology Roadmap for Semiconductor (ITRS) 2005, [online] http://www.itrs.net/
7. Cong J. Challenges and opportunities for design innovations in nanometer technologies, in: Frontiers in Semiconductor Research: A Collection of SRC Working Papers (1997), Semiconductor Research Corp., San Jose, CA
8. Taur Y. CMOS design near the limit of scaling. IBM J. Res. Dev. 46 2/3 (Mar.May 2002) 213-222
9. Fallah F., and Pedram M. Standby and active leakage current control and minimization in CMOS VLSI circuits. IEICE Trans. Electron. E88-C(4) (2005) 509-519
10. J. Kao, S. Narendra, A. Chandrakasan, Subthreshold Leakage Modeling and Reduction Techniques, Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 141-148.
11. S. Mukhopadhyay, H. Mahmoodi-Meimand, C. Neau, K. Roy, Leakage in Nanometer Scale CMOS Circuits, in: International Symposium on VLSI Technology, Systems, and Applications, 2003, pp. 307-312.
12. Walid M., Elgharbawy, Magdy A., and Bayuomi. Leakage Sources and Possible Solutions in Nanometer CMOS Technologies. IEEE Circ. and Systems Mag. 5 4 (2005)
13. Taur Y., Wann C.H., and Frank D.J. 25 nm CMOS Design Considerations. IEDM Tecg. Digest (1998) 789
14. Annema A.J., Nauta B., vanLangevelde R., and Tuinhou H. Analog circuits in ultra-deep-submicron CMOS. IEEE J. solid-state circ. 40 1 (2005)
15. T. Inukai, M. Takamiya, K. Nose, T. Kawaguchi,Boosted Gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. in: Custom Integrated Circuits Conference, 2000, pp. 409-412.
16. Roy K., Mukhopadhyay S., and Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91 2 (2003) 305-327
17. 2 breakdown model for very low voltage lifetime extrapolation. IEEE Trans. Electron. Dev. 41 (1994) 761-767
18. Jan M., Rabaey, Chandrakasan A., and Nikolic B. Digital Integrated Circuits. 2nd ed (2003), Pearson, New Delhi, India
19. H. Kawaguchi, K.-I. Nose, T.A. Sakurai, CMOS scheme for 0.5 V supply voltage with pico-ampere standby current, Digest of Technical Papers. 45th ISSCC 1998 IEEE ISSCC, 5-7 February 1998.
20. th Scaling Scheme for Active Leakage Power Reduction, DATE, 2002. 2002, pp. 163-167.
21. A. Abdollahi, F. Fallah, M. Pedram. Runtime mechanisms for leakage current reduction in CMOS VLSI circuits. in: ISLPED, August 2002.
22. J.P. Halter, F.N. Najm, A gate-level leakage power reduction method for ultra-low-power CMOS circuits. in: IEEE Custom Integrated Circuits Conference, 1997, pp. 442-445.
23. O. Sang-Hyun, Physics technologies of vertical transistors, Ph.D Thesis, Standford, June 2001.
24. Moore G.E. No exponential is forever: but Forever can be delayed!. IEEE International Solid-State Circuits Conference. Digest of Technical Papers 1 (2003) 20-23