Electrical characterization of atomic-layer-deposited hafnium silicate for alternative gate dielectric application

2005 Spanish Conference on Electron Devices, Proceedings

Volumn 2005, Issue , 2005, Pages 45-48

  Duenas S ^a   Castan H ^a   Garcia H ^a   Barbolla, J ^a   Kukli, K ^b,c   Ritala, M ^c   Leskela M ^c  

^a UNIVERSITY OF VALLADOLID   (Spain)

^b UNIVERSITY OF TARTU   (Estonia)

^c UNIVERSITY OF HELSINKI   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CAPACITANCE; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DEPOSITION; GATES (TRANSISTOR); HAFNIUM ALLOYS; INTERFACES (MATERIALS); METALLIZING; SILICA; SILICATES;

ATOMIC LAYER DEPOSITION; CONDUCTANCE TRANSIENT (G-T) TECHNIQUES; HIGH INTERFACIAL STATE;

SEMICONDUCTING FILMS;

EID: 33745697877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SCED.2005.1504302     Document Type: Conference Paper

References (10)

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