Comparison of effective work function extraction methods using capacitance and current measurement techniques

IEEE Electron Device Letters

Volumn 27, Issue 7, 2006, Pages 598-601

  Wen, Huang Chun ^a   Choi, Rino ^a   Brown, George A ^a   Böscke, Tim ^a   Matthews, Kenneth ^a   Harris, Harlan R ^a   Choi, Kisik ^a   Alshareef, Husam N ^a   Luan, Hongfa ^a   Bersuker, Gennadi ^a   Majhi, Prashant ^a   Kwong, Dim Lee ^b   Lee, Byoung Hun ^a  

^a SEMATECH   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Barrier height; High ; Metal gate; Work function

Indexed keywords

CAPACITANCE MEASUREMENT; CORRELATION METHODS; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE STRUCTURES;

BARRIER HEIGHT; CURRENT-VOLTAGE MEASUREMENTS; EFFECTIVE WORK FUNCTION (EWF); METAL GATE;

MOS DEVICES;

EID: 33745652739     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.876324     Document Type: Article

References (16)

1. D. V. Lang, Thermally Stimulated Relaxation in Solids, vol. 37. Berlin, Germany: Springer-Verlag, 1979.
2. R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, "A capacitance-based methodology for work function extraction for metals on high-κ," IEEE Electron Device Lett., vol. 25, no. 6, pp. 420-423, Jun. 2004.
3. P. Majhi, H. C. Wen, H. Alshareef, K. Choi, R. Harris, P. Lysaght, H. Luan, Y. Senzaki, S. C. Song, B. H. Lee, and C. Ramiller, "Evaluation and integration of metal gate electrodes for future generation dual metal CMOS," in Proc. ICICDT, Austin, TX, 2005, pp. 69-72.
4. 2 and high-κ gate stack systems using terraced oxide structures," in Proc. IEEE SISC Conf., 2004, p. 15.
5. H. N. Alshareef, Z. Zhang, P. Majhi, G. Brown, P. Zeitzoff, H. Huff, and B. H. Lee, "Gate electrode development for dual metal-gate CMOS applications," Future Fab, vol. 19, no. 20, pp. 91-93, Jun. 2005.
6. C. C. Hobbs, L. Fonseca, A. Knizhnik, V. Dhandapani, S. B. Samavedam, W. J. Taylor, J. M. Grant, L. G. Dip, D. H. Triyoso, R. I. Hegde, D. C. Gilmer, R. Garcia, D. Roan, M. L. Lovejoy, R. S. Rai, E. A. Hebert, H.-H. Tseng, S. G. H. Anderson, B. E. White, and P. J. Tobin, "Fermi-level pinning at the polysilicon/metal-oxide interface - Part II," IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 978-984, Jun. 2004.
7. 2/Si capacitors," Appl. Phys. Lett., vol. 80, no. 25, pp. 4858-4860, Jun. 2002.
8. S. Zafar, E. Cartier, and E. P. Gusev, "Measurement of barrier heights in high permittivity gate dielectric films," Appl. Phys. Lett., vol. 80, no. 15, pp. 2749-2751, Apr. 2002.
9. 2/metal stacks: Determination of energy level diagram, work functions & their dependence on metal deposition," in VLSI Symp. Tech. Dig., 2005, pp. 44-45.
10. J. R. Hauser and K. Ahmed, "Characterization of ultra-thin oxides using electrical C-V and I-V measurements," presented at the Int. Conf. Characterization Metrology ULSI Technology, Gaithersburg, MD, 1998.
11. + poly-Si gates using chemical oxides and optimized post-annealing," in VLSI Symp. Tech. Dig., 2002, pp. 88-89.
12. T. Hori, Gate Dielectrics and MOS ULSIs Principles, Technologies and Application. Berlin, Germany: Springer-Verlag, 1997.
13. J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," presented at the Int. Conf. Silicon Dielectric Interfaces, Raleigh, NC, 2000.
14. A. A. Demkov, L. R. C. Fonseca, E. Verret, J. Tomfohr, and O. F. Sankey, "Complex band structure and the band alignment problem at the Si-high-κ dielectric interface," Phys. Rev. B, Condens. Matter, vol. 71, no. v.71, p. 195306, 2005.
15. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967.
16. P. Majhi, H.-C. Wen, K. Choi, H. Alshareef, C. Huffman, and B. H. Lee, "A systematic study of the influence of nitrogen in tuning the effective work function of nitrided metal gates," in VLSI Symp. Tech. Dig., 2005, pp. 105-106.