-
2
-
-
24944546345
-
Scalable custom instructions identification for instruction-set extensible processors
-
Washington, D.C., Sept.
-
Pan Yu and Tulika Mitra: Scalable Custom Instructions Identification for Instruction-Set Extensible Processors. Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Washington, D.C., Sept. 2004.
-
(2004)
Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
-
-
Yu, P.1
Mitra, T.2
-
5
-
-
0033488529
-
ConCISe: A compiler-driven CPLD-based instruction set accelerator
-
Napa Valley, Calif., Apr.
-
B.Kastrup, A. Bink, and J. Hoogerbrugge: ConCISe: A Compiler-Driven CPLD-based Instruction Set Accelerator. Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif., Apr. 1999.
-
(1999)
Proceedings of the 7th IEEE Symposium on Field-programmable Custom Computing Machines
-
-
Kastrup, B.1
Bink, A.2
Hoogerbrugge, J.3
-
6
-
-
25544447955
-
On the limits of processor specialisation by mapping dataflow sections on ad-hoc functional units
-
Swiss Federal Institute of Technology Lausanne, Computer Science Department, Dec.
-
P.Ienne, L. Pozzi, and M. Vuletic: On the Limits of Processor Specialisation by Mapping Dataflow Sections on Ad-hoc Functional Units. Technical Report 01/376, Swiss Federal Institute of Technology Lausanne, Computer Science Department, Dec. 2001.
-
(2001)
Technical Report
, vol.1
, Issue.376
-
-
Ienne, P.1
Pozzi, L.2
Vuletic, M.3
-
8
-
-
33646927796
-
ISEGEN: Generation of high-quality instruction set extensions by iterative improvement
-
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. Design Automation and Test in Europe (DATE), 2005.
-
(2005)
Design Automation and Test in Europe (DATE)
-
-
Biswas, P.1
Banerjee, S.2
Dutt, N.D.3
Pozzi, L.4
Ienne, P.5
-
9
-
-
20344403542
-
Instruction set extension with shadow registers for configurable processors
-
Feb.
-
J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman and Z. Zhang: Instruction Set Extension with Shadow Registers for Configurable Processors. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, Feb. 2005.
-
(2005)
Proceedings of the ACM International Symposium on Field-programmable Gate Arrays
-
-
Cong, Y.1
Fan, G.2
Han, A.3
Jagannathan, G.4
Reinman, J.5
Zhang, Z.6
-
10
-
-
4444384247
-
Characterizing embedded applications for instruction-set extensible processors
-
June
-
Pan Yu and Tulika Mitra: Characterizing Embedded Applications for Instruction-Set Extensible Processors. 41st ACM/IEEE Design Automation Conference (DAC), June 2004.
-
(2004)
41st ACM/IEEE Design Automation Conference (DAC)
-
-
Yu, P.1
Mitra, T.2
-
12
-
-
33745616829
-
-
SimpleScalar LLC, http://www.simplescalar.com.
-
-
-
-
14
-
-
84903174410
-
-
MediaBench, http://cares.ucsl.ucla.edu/MediaBench/.
-
MediaBench
-
-
-
18
-
-
2442575888
-
A quantitative analysis of the speedup factors of FPGas over processors
-
Monterey, California, USA, February
-
Zhi Guo, Walid Najjar, Frank Vahid, Kees Vissers: A Quantitative Analysis of The Speedup Factors of FPGAs over Processors. Proceeding of the 2004 ACM/SIGDA 12th international Symposium on Field programmable Gate Arrays, Monterey, California, USA, February 2004.
-
(2004)
Proceeding of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays
-
-
Zhi, G.1
Najjar, W.2
Vahid, F.3
Vissers, K.4
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