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Volumn 2005, Issue , 2005, Pages 309-312

Evaluation of SET and SEU effects at multiple abstraction levels

Author keywords

[No Author keywords available]

Indexed keywords

EVALUATION; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS;

EID: 33745502880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.28     Document Type: Conference Paper
Times cited : (16)

References (9)
  • 1
    • 0033314263 scopus 로고    scopus 로고
    • Soft error considerations for deep submicron CMOS circuit applications
    • N. Cohen et al. "Soft Error Considerations for Deep Submicron CMOS Circuit Applications", Int. Electron Devices Meeting, 1999, pp. 315-318.
    • (1999) Int. Electron Devices Meeting , pp. 315-318
    • Cohen, N.1
  • 2
    • 0036931372 scopus 로고    scopus 로고
    • Modeling the effect of technology trends on the soft error rate of combinational logic
    • P. Shivakumar et al, "Modeling the Effect of technology Trends on the Soft Error Rate of Combinational Logic", Int. Conference of Dependable Systems and Networks, 2002, pp. 389-398.
    • (2002) Int. Conference of Dependable Systems and Networks , pp. 389-398
    • Shivakumar, P.1
  • 3
    • 0141630235 scopus 로고    scopus 로고
    • Multi-level fault injections in VHDL descriptions: Alternative approaches and experiments
    • Oct.
    • R. Leveugle, K. Hadjiat, "Multi-level fault injections in VHDL descriptions: alternative approaches and experiments", Journal of Electronic Testing: Theory and Applications, vol. 19, no. 5, Oct. 2003, pp. 559-575
    • (2003) Journal of Electronic Testing: Theory and Applications , vol.19 , Issue.5 , pp. 559-575
    • Leveugle, R.1    Hadjiat, K.2
  • 5
    • 0036605167 scopus 로고    scopus 로고
    • An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits
    • June
    • P. Civera et al., "An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits", Journal of Electronic Testing: Theory and Applications, vol. 18, no. 3, June 2002, pp. 261-271
    • (2002) Journal of Electronic Testing: Theory and Applications , vol.18 , Issue.3 , pp. 261-271
    • Civera, P.1
  • 7
  • 8
    • 35148887860 scopus 로고    scopus 로고
    • Reliability properties assessment at system level: A co-design framework
    • C. Bolchini et al., "Reliability properties assessment at system level: a co-design framework", 7th IEEE Int. On-Line Testing workshop, 2001, pp. 165-171
    • (2001) 7th IEEE Int. On-Line Testing Workshop , pp. 165-171
    • Bolchini, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.