A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding

Semiconductor Science and Technology

Volumn 21, Issue 7, 2006, Pages 959-963

  Ma, Xiaobo ^a,b   Liu, Weili ^a   Chen, Chao ^a,b   Zhan, Da ^a,b   Song, Zhitang ^a   Feng, Songlin ^a  

^a SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ETCHING; PLASMAS; SILICON WAFERS; SURFACE ROUGHNESS; THERMAL EFFECTS;

CO-IMPLANTATION; CRITICAL TEMPERATURE; DEFECT DENSITY; SPLITTING TEMPERATURE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 33745278235     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/21/7/022     Document Type: Article

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