Semi-formal verification of VHDL-AMS descriptions

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Salem, Ashraf ^a  

^a Ain Shams University   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; ANALOG TO DIGITAL CONVERSION; COMPARATOR CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FORMAL LANGUAGES; SYNTACTICS;

ANALOG MIXED SIGNAL; BINARY DECISION DIAGRAMS; BOOLEAN SATISFIABILITY; EQUIVALENCE CHECKER; FUNCTIONAL VERIFICATION; MITER CIRCUITS; SYNTACTIC MATCHING; SYSTEM ON CHIP;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0036287736     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Analog and mixed signal hardware description languages
2. Mixed-mode simulation and analog multilevel simulation
3. An architecture of distributed VHDL-AMS simulator
4. M-CHECK: A multiple engine combinational equivalence checker
5. Formal verifications of VHDL descriptions in the prevail environment
6. Verification of large synthesized designs
7. Test pattern generation using Boolean satisfiability
8. Graph-based algorithms for Boolean function manipulation
9. Equations and rewrite rules, a survey
10. Varieties of if-then-else
11. Formal semantics of VHDL timing constructs