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Volumn , Issue , 1997, Pages 432-436

A symbolic core approach to the formal verification of integrated mixed-mode applications

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SYSTEM DESIGN; FORMAL APPROACH; FUNCTIONAL CORRECTNESS; MIXED MODE; MIXED-MODE SYSTEMS; MODELLING TECHNIQUES; SIMULATION BASED VERIFICATION; DIGITAL SYSTEM; SYMBOLIC MODELING;

EID: 85029616841     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1997.582396     Document Type: Conference Paper
Times cited : (1)

References (13)
  • 1
    • 0040583548 scopus 로고    scopus 로고
    • SmartPen - An application of integrated microsystems and embedded hardware/software CoDesign
    • Paris, IEEE Computer Society
    • L. Claesen, D. Beullens, R. Martens, et al., "SmartPen - An Application of Integrated Microsystems and Embedded Hardware/Software CoDesign", In: IEEE Users Forum of ED&TC, Paris 1996, IEEE Computer Society, pp. 201-205.
    • (1996) IEEE Users Forum of ED&TC , pp. 201-205
    • Claesen, L.1    Beullens, D.2    Martens, R.3
  • 2
    • 85029623887 scopus 로고    scopus 로고
    • A symbolic modelling approach for the formal verification of integrated mixed-mode systems
    • 2-4 September, Bastad Sweden
    • Stefan Hendricx, Luc Claesen, "A Symbolic Modelling Approach for the Formal Verification of Integrated Mixed-Mode Systems", In: Proc. 3rd Designing Correct Circuits Workshop, 2-4 September 1996, Bastad (Sweden).
    • (1996) Proc. 3rd Designing Correct Circuits Workshop
    • Hendricx, S.1    Claesen, L.2
  • 3
    • 84898794193 scopus 로고    scopus 로고
    • On-line signature verification by dynamic time-warping
    • IEEE Computer Society, August 25-29, Vienna
    • R. Martens, L. Claesen, "On-Line Signature Verification by Dynamic Time-Warping", In: Proc. 13th International Conference on Pattern Recognition, Vol. Ill, pp. 38-42, IEEE Computer Society, August 25-29, 1996, Vienna.
    • (1996) Proc. 13th International Conference on Pattern Recognition , vol.99 , pp. 38-42
    • Martens, R.1    Claesen, L.2
  • 4
    • 0002377851 scopus 로고
    • Automatic signature verification: The state of the art - 1989-1993
    • Artificial Intelligence
    • F. Leclerc, R. Plamondon, "Automatic Signature Verification: The State Of The Art - 1989-1993", In: Int. Journal on Pattern Recognition. Artificial Intelligence, vol. 8, pp.643-660, 1994.
    • (1994) Int. Journal on Pattern Recognition , vol.8 , pp. 643-660
    • Leclerc, F.1    Plamondon, R.2
  • 6
    • 0028500611 scopus 로고
    • Mixed analog-digital simulation
    • September
    • D. Conner. "Mixed Analog-Digital Simulation", In: EDN 1994 (September), pp. 39-44.
    • (1994) EDN , pp. 39-44
    • Conner, D.1
  • 9
    • 0024036029 scopus 로고
    • Formal verification of hardware correctness: Introduction and survey of current research
    • July
    • P. Camurati and P. Prinetto. "Formal Verification of Hardware Correctness: Introduction and Survey of Current Research" In: IEEE Computer 1988 (July), 8-19.
    • (1988) IEEE Computer , pp. 8-19
    • Camurati, P.1    Prinetto, P.2
  • 10
    • 85029629475 scopus 로고    scopus 로고
    • An integrated approach to verifying large circuits : A case study
    • 2-4 September, Bilstad Sweden
    • S. Hazelhurst, C-J. H. Seger. "An Integrated Approach to Verifying Large Circuits : A Case Study", In: Proc. 3rd Designing Correct Circuits Workshop, 2-4 September 1996, Bilstad (Sweden).
    • (1996) Proc. 3rd Designing Correct Circuits Workshop
    • Hazelhurst, S.1    Seger, C.-J.H.2
  • 12
    • 0343946038 scopus 로고
    • SFG- Tracing: A methodology for the automatic verification of MOS transistor level implementations from high level behavioural specifications
    • ed. P. A. Subrahmanyam
    • L. Claesen, F. Proesmans, E. Verlind, H. De Man. "SFG- Tracing: A Methodology for the Automatic Verification of MOS Transistor Level Implementations from High Level Behavioural Specifications", In: Proceedings ACM- SIGDA International Workshop on Formal Methods in VLSI Design (ed. P. A. Subrahmanyam), 1991.
    • (1991) Proceedings ACM- SIGDA International Workshop on Formal Methods in VLSI Design
    • Claesen, L.1    Proesmans, F.2    Verlind, E.3    Man, H.D.4
  • 13
    • 0026291944 scopus 로고    scopus 로고
    • Illustration of the SFG-tracing multi-level behavioural verification methodology, by the correctness proof of a high to low level synthesis application in CATHEDRAL-II
    • M. Genoe, L. Claesen, E. Proesmans, E. Verlind, H. De Man. "Illustration of the SFG-Tracing Multi-Level Behavioural Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II", In: Proc. ICCD-91.
    • Proc. ICCD-91
    • Genoe, M.1    Claesen, L.2    Proesmans, E.3    Verlind, E.4    Man, H.D.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.