Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation

Analog Integrated Circuits and Signal Processing

Volumn 21, Issue 3, 1999, Pages 271-296

  Serrano Gotarredona, Teresa ^a   Linares Barranco, Bernabé ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; COMPUTER SIMULATION; CORRELATION METHODS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; THRESHOLD VOLTAGE;

ANALOG INTEGRATED CIRCUITS; TRANSISTOR MISMATCH;

CMOS INTEGRATED CIRCUITS;

EID: 0033350671     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008330121404     Document Type: Article

References (19)

1. F. Medeiro, R. Rodríguez-Macías, F. V. Fernández, R. Domínguez-Castro, and A. Rodríguez-Vãzquez, "Global analogue cell design and optimization using statistical techniques." Analog Integrated Circuits and Signal Processing 6, pp. 179-195, 1994.
2. M. G. R. Degrauwe et al., "IDAC: An interactive design tool for analog CMOS Circuits." IEEE Journal of Solid-State Circuits 22, pp. 1106-1114, 1987.
3. F. El-Turky and E. E. Perry, "Blades: An artificial intelligence approach to analog circuits design." IEEE Trans. on computer-Aided Design 8, pp. 680-691, 1989.
4. R. Harjani, R. Rutenbar, and L. R. Carley, "OASYS: A framework for analog circuits synthesis." IEEE Trans. on Computer-Aided Design 8, pp. 1247-1265, 1989.
5. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors." IEEE Journal of Solid-State Circuits 24(5), pp. 1433-1440, 1989.
6. K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transitors for precision analog design." IEEE Journal of Solid-State Circuits SC-21(6), pp. 1057-1066, 1986.
7. J. B. Shyu, G. C. Temes, and F. Krummenacher, "Random error effects in matched MOS capacitors and current sources." IEEE Journal of Solid-State Circuits SC-19, pp. 948-955, 1984.
8. J. Bastos, M. Steyaert, R. Roovers, P. Kinger, W. Sansen, B. Graindourze, A. Pergoot, and E. Janssens, "Mismatch characterization of small size MOS transistors." Proc. IEEE 1995 Int. Conf. Microelectronic Test Structures, 8, pp. 271-276, 1995.
9. J. Bastos, M. Steyaert, A. Pergoot, and W. E. Sansen, "Mismatch characterization of submicron MOS transistors." Analog Integrated Circuits and Signal Processing 12, pp. 95-106, 1997.
10. J. Bastos, Characterization of MOS Transistor Mismatch for Analog Design. Ph.D. Dissertation, Katholieke Universiteit Leuven, 1998.
11. C. Michael and M. Ismail, "Statistical modeling of device mismatch for analog MOS integrated circuits." IEEE Journal of Solid-State Circuits 27(2), pp. 154-166, 1992.
12. A. Pavasovic, A. G. Andreou, and C. R. Westgate, "Characterization of subthreshold MOS mismatch transistors for VLSI systems." Analog Integrated Circuits and Signal Processing 8, pp. 75-85, Kluwer Academics, 1994.
13. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. Holt, Rinehart and Winston, Inc., New York, 1987.
14. T. Serrano-Gotarredona and B. Linares-Barranco, "Cheap and easy systematic CMOS transistor mismatch characterization." Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (ISCAS'98), Monterrey, California, 1998.
15. Lennart Rade and Bertil Westergren, BETA Mathematics Handbook. CRC Press, Boca 1990.
16. W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C. The Art of Computing. Cambridge University Press, Cambridge 1988.
17. Y. Tsividis, Operation and Modeling of the MOS Transistor. McGraw-Hill, New York, 1988.
18. U. Cilingiroglu, Systematic Analysis of Bipolar and MOS Transistors. Artech House, Boston, 1993.
19. R. W. Gregor, "On the relationship between topography and transistor matching in an analog CMOS technology." IEEE Trans. on Electron Devices 39(2), pp. 275-282, 1992.