Impact of metal work function on memory properties of charge-trap Flash memory devices using Fowler-Nordheim P/E mode

IEEE Electron Device Letters

Volumn 27, Issue 6, 2006, Pages 486-488

  Jeon, Sanghun ^a,b   Han, Jeong Hee ^a,b   Lee, Junghoon ^a   Choi, Sangmoo ^c   Hwang, Hyunsang ^c   Kim, Chungwoo ^a,b  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Gwangju Institute of Science and Technology (GIST)   (South Korea)

Author keywords

Charge trap; Electron back tunneling (EBT); Hole back tunneling (HBT); Work function

Indexed keywords

ALUMINA; DATA STORAGE EQUIPMENT; ELECTRON TRAPS; ELECTRON TUNNELING; SILICA; SILICON NITRIDE;

CHARGE TRAP; ELECTRON BACK TUNNELING; HOLE BACK TUNNELING; METAL WORK FUNCTION;

FLASH MEMORY;

EID: 33744718803     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.874216     Document Type: Article

References (10)

1. J.-D. Lee, S.-H. Hur, and J.-D. Choi, "Effects of floating-gate interference on NAND Flash memory cell operation," IEEE Electron Device Lett., vol. 23, no. 5, pp. 264-266, May 2002.
2. M. H. White, D. A. Adams, and J. Bu, "On the go with SONOS," IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22-31, Jul. 2000.
3. M. K. Cho and D.M. Kim, "High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current Flash technology," IEEE Electron Device Lett., vol. 21, no. 8, pp. 399-401, Aug. 2000.
4. C. W. Oh, S. D. Suk, Y. K. Lee, S. K. Sung, J.-D. Choe, S.-Y. Lee, D. U. Choi, K. H. Yeo, M. S. Kim, S.-M. Kim, M. Li, S. H. Kim, E.-J. Yoon, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, "Damascene gate FinFET SONOS memory implemented on bulk silicon wafer," in IEDM Tech. Dig., Dec. 2004, pp. 893-896.
5. V. A. Gritsenko, K. A. Nasyrov, Y. N. Novikov, A. L. Aseev, S. Y. Yoon, J.-W. Lee, E.-H. Lee, and C. W. Kim, "A new low voltage fast SONOS memory with high-κ dielectric," Solid State Electron., vol. 47, no. 10, pp. 1651-1656, Oct. 2003.
6. 3 with TaN metal gate for multi-giga bit Flash memories," in IEDM Tech. Dig., Dec. 2003, pp. 613-616.
7. H. Reisinger, M. Franosch, B. Hasle, and T. Bohm, "A novel SONOS structure for nonvolatile memories with improved data retention," in VLSI Symp. Tech. Dig., Jun. 1997, pp. 113-114.
8. H.-J. Cho, H. L. Lee, S. G. Park, H. B. Park, T. S. Jeon, B. J. Jin, S. B. Kanng, S. G. Lee, Y. P. Kim, I. S. Jung, J. W. Lee, J. H. Choi, Y. S. Jeon, Y. G. Shin, U.-I. Chung, and J. T. Moon, "The effect of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs," in IEDM Tech. Dig., 2004, pp. 503-506.
9. D.-G. Park, T.-H. Cha, K.-Y. Lim, H.-J. Cho, T.-K. Kim, S.-A. Jang, Y.-S. Sug, V. Mirsa, I.-S. Yeo, J.-S. Roh, J. W. Park, and H.-K. Yoon, "Robust ternary metal gate electrodes for dual gate CMOS devices," in IEDM Tech. Dig., 2001, pp. 671-674.
10. D.-G. Park, "Thermally robust dual-work function ALD-MN MOSFET's using conventional CMOS process flow," in VLSI Symp. Tech. Dig., 2004, pp. 186-187.