System-in-package testing: Problems and solutions

IEEE Design and Test of Computers

Volumn 23, Issue 3, 2006, Pages 203-211

  Appello, Davide ^a   Bernardi, Paolo ^b   Grosso, Michelangelo ^b   Reorda, Matteo Sonza ^b  

^a STMICROELECTRONICS   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; PRODUCT DESIGN; SUBSTRATES;

MULTIPLE DIE; SYSTEM-IN-PACKAGE;

CHIP SCALE PACKAGES;

EID: 33744549297     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.79     Document Type: Article

References (11)

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