메뉴 건너뛰기




Volumn , Issue , 2003, Pages 7-10

The reliability issues on ASIC/memory integration by SiP (system-in-package) technology

Author keywords

Application specific integrated circuits; Bonding; Earth Observing System; Energy consumption; Integrated circuit reliability; Large scale integration; Leakage current; Packaging; Routing; SDRAM

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BONDING; ELECTROMAGNETIC PULSE; ENERGY UTILIZATION; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LSI CIRCUITS; PACKAGING; PRINTED CIRCUIT BOARDS; PRINTED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; RELIABILITY;

EID: 33744511660     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241451     Document Type: Conference Paper
Times cited : (6)

References (6)
  • 1
    • 0042969330 scopus 로고    scopus 로고
    • A study of advanced layout verification to prevent leakage current failure during power down mode operation
    • Yong-Ha Song, M.L.Park, G.W.Jung, T.S. Kim, "A study of advanced layout verification to prevent leakage current failure during power down mode operation", ESREF, 2002, pp 1385-1388.
    • (2002) ESREF , pp. 1385-1388
    • Song, Y.-H.1    Park, M.L.2    Jung, G.W.3    Kim, T.S.4
  • 5
    • 0033221989 scopus 로고    scopus 로고
    • High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process
    • Gajendra P. Singh, Raoul B, Salem "High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process", IEEE journal of solid-state circuits, 1999, pp 1512-1525
    • (1999) IEEE Journal of Solid-state Circuits , pp. 1512-1525
    • Singh, G.P.1    Salem, R.B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.