Double bump flip-chip assembly

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 29, Issue 2, 2006, Pages 119-133

  Yan, Kathy W ^a,b   Johnson, R Wayne ^a   Stapleton, Russell ^c   Ghosh, Kalyan ^c  

^a AUBURN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c LORD CORPORATION   (United States)

Author keywords

Flip chip; Flip chip assembly; Flip chip modeling; Flip chip reliability; Preapplied underfill

Indexed keywords

ASSEMBLY; ELECTRONICS PACKAGING; PRINTED CIRCUIT BOARDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; THERMAL EXPANSION;

FLIP-CHIP ASSEMBLY; FLIP-CHIP MODELING; FLIP-CHIP RELIABILITY; PREAPPLIED UNDERFILL;

FLIP CHIP DEVICES;

EID: 33744479187     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2006.872689     Document Type: Article

References (21)

1. N. Matsui, S. Sasaki, and T. Ohsaki, "VLSI chip interconnection technology using stacked solder bumps," IEEE Trans. Compon., Hybrids, Manuf. Technol., vol. CHMT-12, no. 4, pp. 566-580, Dec. 1987.
2. F. Lovasco and M. A. Oien, "Double-bump surface-mount technology for very high IO interconnections," in Proc. 4th IEEE/CHMT Eur. Int. for Electron. Manuf. Technol., Jun. 13-15, 1988, pp. 41-44.
3. J. Simon and H. Riechl, "Board level reliability of a waferlevel CSP using stacked solder spheres and a Solder Support Structure (S3)," in Proc. 50th Electron. Compon. Technol. Conf., Las Vegas, NV, May 21-24, 2000, pp. 81-86.
4. M. Topper, J. Auersper, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jager, D. Petter, and O. Ehrmann, "Fab Integrated Packaging (FIP): A new concept for high reliability wafer-level chip size packaging," in Proc. Elect. Compon. Technol. Conf., Las Vegas, NV, May 21-24, 2000, pp. 74-80.
5. B. Keser, B. Yeung, J. White, and T. Fang, "Encapsulated double-bump WL-CSP: Design and reliability," in Proc. Elect. Compon. Technol. Conf., Orlando, FL, May 29-Jun. 1 2001, pp. 35-39.
6. V. Patwardhan, H. Nguyen, L. Zhang, N. Kelkar, and L. Nguyen, "Constrained collapse solder joint formation for wafer-level-chip-scale packages to achieve reliability improvement," in Proc. 54th Elect. Compon. Technol. Conf., New Orleans, LA, Jun. 1-4, 2004, pp. 1479-1485.
7. R. Pennisi, "Adhesive and Encapsulant Material With Fluxing Properties," U.S. Patent 5 128 746, Sep. 27, 1990.
8. D. Milner, C. Paydenkar, and D. F. Baldwin, "Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials," in Proc. IPC APEX Conf., San Diego, CA, Jan. 19-24, 2002, pp. S18-2-1-S18-2-7.
9. R. Zhao, R. W. Johnson, G. Jones, E. Yaeger, M. Konarski, P. Krug, and L. Crane, "Processing of fluxing underfills for flip chip-on-laminate assembly," IEEE Trans. Elect. Packag. Manuf., vol. 26, no. 1, pp. 75-83, Jan. 2003.
10. M. Colella and D. Baldwin, "Near void free hybrid no-flow underfill flip chip process technology," in Proc. 54th Electron. Compon. Technol. Conf., Las Vegas, NV, Jun. 2-4, 2004, pp. 780-788.
11. A. Grieve, M. A. Capote, H. A. Lenos, and A. Soriano, "Low-cost, wafer level underfilling and reliability testing of flip chip devices," in Proc. 54th Elect. Compon. Technol. Conf., Las Vegas, NV, Jun. 2-4, 2004, pp. 1492-1498.
12. K. Brakke, The Surface Evolver Manual, Math. Dept., Susquehanna Univ. Selinsgrove, PA. 2.2 ed., 1992.
13. Y. Zhang, R. Zhao, D. K. Harris, and R. W. Johnson, "A computational study on solder bump geometry, normal, restoring, and fillet forces during solder reflow in the presence of liquefied underfill," IEEE Trans. Elect. Packag. Manuf., vol. 25, no. 4, pp. 308-317, Oct. 2002.
14. Cookson Electronics Alpha Stencils, Stencil Design Guidelines [Online]. Available: http://www.alphametals.com/products/stencils/design_guide.html
15. S. Wiese, S. Jakschik, F. Feustel, and E. Meusel, "Fracture behavior of flip chip solder joints," in Proc. 51st Elect. Compon. Technol. Conf., Orlando, FL, May 29-Jun. 1 2001, pp. 890-902.
16. B. A. Zahn, "Solder joint fatigue life model methodology for 63Sn 337Pb and 95.5Sn4Ag0.5Cu materials," in Proc. 53rd Elect. Compon. Technol. Conf., May 27-30, 2003, pp. 83-94.
17. R. Darveaux, "Effect of simulation methodology on solder joint crack growth correlation," in Proc. 50th Elect. Compon. Technol. Conf., Las Vegas, NV, May 21-24, 2000, pp. 1048-1058.
18. W. Engelmaier, "Surface mount solder joint reliability: Controlling the thermal expansion mismatch problem," in Proc. Electron. Manuf. Technol. Symp. 4th IEEE/CHMT Eur. Int., Jun. 13-15, 1988, pp. 62-65.
19. W. Engelmaier, "Solder joints in electronics design for reliability," in Keynote Address in Design and Reliability of Solder and Solder Interconnectons, 1997, pp. 9-19.
20. H. D. Solomon, "Fatigue of 60/40 solder," IEEE Trans. Compon., Packag. Manuf. Technol., vol. CHMT-9, no. 4, pp. 423-433, Dec. 1986.
21. X. Q. Shi, H. L. J. Pang, W. Zhou, and Z. P. Wang, "A modified energy-based low cylce fatigue model for eutectic solder alloy," Scripta Mater., vol. 41, pp. 289-296, 1999.