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Volumn 25, Issue 4, 2002, Pages 308-317

A computational study on solder bump geometry, normal, restoring, and fillet forces during solder reflow in the presence of liquefied underfill

Author keywords

Fillet forces; Flip chip; Reflow; Solder bump; Surface evolver; Underfill

Indexed keywords

FLIP CHIP DEVICES; MATHEMATICAL MODELS; MECHANICAL PROPERTIES; REGRESSION ANALYSIS; SOLDERING ALLOYS; SURFACE TENSION; WELDS; WETTING;

EID: 0036826623     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2002.801371     Document Type: Article
Times cited : (7)

References (12)
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    • Katyl, R.H.1    Pimbley, W.T.2
  • 6
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    • Patra, S.K.1    Lee, Y.C.2
  • 7
    • 0026407890 scopus 로고
    • Modeling of self-alignment mechanism in flip-chip soldering-Part II: Multichip solder joints
    • May 11-16
    • ____ and ____ "Modeling of self-alignment mechanism in flip-chip soldering-Part II: Multichip solder joints," Proc. IEEE, pp. 783-788, May 11-16, 1991.
    • (1991) Proc. IEEE , pp. 783-788
    • Patra, S.K.1    Lee, Y.C.2
  • 8
    • 0029358567 scopus 로고
    • Design of solder joints for self-aligned optoelectronic assemblies
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    • W. Lin, S. K. Patra, and Y. C. Lee, "Design of Solder Joints for Self-Aligned Optoelectronic Assemblies," IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 18, pp., 543-551, Aug. 1995.
    • (1995) IEEE Trans. Comp., Packag., Manufact. Technol. B , vol.18 , pp. 543-551
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  • 9
    • 0033311132 scopus 로고    scopus 로고
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    • S. C. Tower, B. Su, and Y. C. Lee, "Yield Prediction for Flip-Chip solder Assemblies Based on Solder Shape Modeling," IEEE Trans. Electron. Packag. Manufact., vol. 22, pp. 29-37, Jan. 1999.
    • (1999) IEEE Trans. Electron. Packag. Manufact. , vol.22 , pp. 29-37
    • Tower, S.C.1    Su, B.2    Lee, Y.C.3
  • 10
    • 0028681881 scopus 로고
    • Mathematic modeling of alternative pad designs in flip-chip soldering processed
    • Dec.
    • S. E. Deering and J. Szekely, "Mathematic Modeling of Alternative Pad Designs in Flip-Chip Soldering Processed," J. Electron. Mater., vol. 23, pp. 1325-1334, Dec. 1994.
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    • Deering, S.E.1    Szekely, J.2
  • 12
    • 4244129614 scopus 로고    scopus 로고
    • Modeling of the wafer applied underfill flip chip process
    • M.S. thesis, Auburn Univ., Auburn, AL
    • Y. Zhang,"Modeling of the wafer applied underfill flip chip process," M.S. thesis, Auburn Univ., Auburn, AL, 2000.
    • (2000)
    • Zhang, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.