Constrained collapse solder joint formation for wafer-level-chip-scale packages to achieve reliability improvement

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1479-1485

  Patwardhan, V ^a   Nguyen, H ^a   Zhang, L ^a   Kelkar, N ^a   Nguyen, L ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL PERFORMANCE; PIN-COUNT RANGE; SOLDER BUMPS; UNDERFILLS;

CRACKS; PRINTED CIRCUIT BOARDS; RELIABILITY; SEMICONDUCTOR MATERIALS; SOLDERED JOINTS; SURFACE MOUNT TECHNOLOGY; THERMAL LOAD; THICKNESS MEASUREMENT;

CHIP SCALE PACKAGES;

EID: 10444252609     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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