On applying incremental satisfiability to delay fault testing

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 380-384

  Kim, Joonyoung ^a   Whittemore, Jesse ^a   Marques Silva, João P ^b   Sakallah, Karem ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN SATISFIABILITY PROBLEMS; DELAY-FAULT TESTING; ELECTRONIC DESIGN AUTOMATION; INCREMENTAL SATISFIABILITY; LOGIC VERIFICATION; PATH SENSITIZATION; SAT INSTANCES; TIMING ANALYSIS;

EXHIBITIONS; FORMAL LOGIC;

DELAY CIRCUITS;

EID: 0003934656     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840299     Document Type: Conference Paper

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