Using BDDs and ZBDDs for efficient identification of testable path delay faults

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 50-55

  Padmanaban, Saravanan ^a   Tragoudas, Spyros ^b  

^a UNIVERSITY OF MARYLAND BALTIMORE COUNTY   (United States)

^b SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS; DELAY FAULT TESTS; PATH DELAY FAULTS; TEST GENERATION; DECISION DIAGRAM; FAN-OUT; PATH DELAY FAULT; UNTESTABLE PATH;

AUTOMATIC TESTING; COMPUTER SIMULATION; DECISION MAKING; DELAY CIRCUITS; PROBLEM SOLVING; REDUNDANCY; ROBUSTNESS (CONTROL SYSTEMS); BOOLEAN FUNCTIONS; EXHIBITIONS;

ELECTRIC FAULT CURRENTS;

EID: 3042610070     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268826     Document Type: Conference Paper

References (12)

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