Path delay fault test generation for standard scan designs using state tuples

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 767-772

  Shao, Yun ^a   Pomeranz, I ^b   Reddy, S M ^a  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC FAULT CURRENTS; TESTING;

HIGH-EFFICIENCY; IMPLEMENTATION COMPLEXITY; NOVEL CONCEPT; PATH DELAY FAULT; SCAN DESIGNS;

DESIGN;

EID: 3142756244     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995026     Document Type: Conference Paper

References (18)

1. G. L. Smith, "Model for Delay Faults Based Upon Paths", Proc ITC, pp. 342-349, September 1985.
2. J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyengar, "Transition Fault Simulation", IEEE Design and Test, pp. 32-38, April 1987.
3. A. K. Pramanick and S.M. Reddy, "On the Computation of the Ranges of Detected Delay Fault Sizes," Proc. ICCAD, pp. 126-129, November 1989.
4. V. S. Iyengar, B. K. Rosen, and J. A. Waicukauski, "On computing the sizes of detected delay faults", IEEE TCAD, pp. 299-312, March 1990.
5. C. J. Lin and S. M. Reddy, "On Delay Fault Testing in Logic Circuits", IEEE TCAD, pp. 694-703, September 1987.
6. K. T. Cheng and H.-C. Chen, "Delay Testing For Non-Robust Untestable Circuits", Proc. ITC., pp. 954-961, October 1993.
7. K. Fuchs, F. Fink, and M. H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults", IEEE TCAD, pp. 1323-1335, October 1991.
8. K.-T. Cheng, S. Devadas, and K. Keutzer, "Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology", IEEE TCAD, pp. 1217-1231, August 1993.
9. K. Fuchs, M. Pabst, and T. Rossel, "RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults Considering Various Test Classes", IEEE TCAD, pp. 1550-1562, December 1994.
10. B. Underwood, W. O. Law, S. Kang, and H. Konuk, "Fastpath: A Path-Delay Test Generator for Standard Scan Designs", Proc. ITC, pp. 154-163, October 1994.
11. P. Varma, "On Path Delay Testing in a Standard Scan Environment", Proc. ITC., pp. 164-173, October 1994.
12. S. Bose, P. Agrawal, and V. D. Agrawal, "Generation of Compact Delay Tests by Multiple Path Activation", Proc. ITC, pp. 714-723, October 1993.
13. S. Bose, P. Agrawal, and V. D. Agrawal, "Deriving Logic Systems for Path Delay Test Generation", IEEE Trans. on Computers, pp. 829-846, August 1998.
14. A. K. Majhi and V. D. Agrawal, "Tutorial: Delay Fault Models and Coverage", Proc. 11th Int'l Conf. on VLSI Design, pp. 364-369, January 1998.
15. M. H. Schulz, F. Fink, and K. Fuchs, "Parallel Pattern Fault Simulation of Path Delay Faults", Proc. 26th DAC., pp. 357-363, June 1989.
16. P. Goel, "An implicit enumeration algorithm to generate tests for combinational logic circuits", IEEE Trans. on Computers, pp. 215-222, March 1981.
17. T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell, "Delay Fault Models and Test Generation", Proc. 29th DAC, pp. 165-172, June 1992.
18. R. Desineni, K. N. Dwarkanath, R. D. Blanton, "Universal Test Generation Using Fault Tuples", Proc. ITC, pp. 812-819, October 2000.