Why interconnect prediction doesn't work

International Workshop on System-Level Interconnect Prediction (SLIP 2000)

Volumn , Issue , 2000, Pages 139-144

  Scheffer, Lou ^a   Nequist, Eric ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Constructive estimation; Interconnect prediction; Wire load model

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC WIRE; ESTIMATION; MICROPROCESSOR CHIPS; ROUTERS;

WIRE LOAD MODEL;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034592340     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/333032.333044     Document Type: Conference Paper

References (6)

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2. Trimberger, S., 'A Reprogrammable Gate Array and Applications', Proceedings of the IEEE, Volume: 81 7, July 1993, Page(s): 1030-1041.
3. "Tool tightens layout link, ditches wire-load model - Cadence lays claim to synthesis coup", Electronic Engineering Times, July 12, 1999
4. "Synthesis takes two giant steps: Synopsys' long-awaited Physical Compiler unites placement with synthesis", Electronic Engineering Times, Nov. 15, 1999
5. "Cadence triggers synthesis price war", Electronic Engineering Times, September 13, 1999
6. "Nano Project would reroute today's synthesis-to-layout flow - Cadence maps design overhaul", Electronic Engineering Times, May 17, 1999