Doubling speed using strained Si/SiGe CMOS technology

Thin Solid Films

Volumn 508, Issue 1-2, 2006, Pages 338-341

  Olsen, Sarah H ^a   Temple, Matthew ^b   O'Neill, Anthony G ^a   Paul, Douglas J ^b   Chattopadhyay, Sanatan ^a   Kwa, Kelvin S K ^a   Driscoll, Luke S ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

CMOS; Gate delay; Strained silicon; Technology

Indexed keywords

COSTS; GERMANIUM; MOSFET DEVICES; SILICON; SUBSTRATES; THIN FILMS; TRANSCONDUCTANCE;

GATE DELAY; STRAINED-SILICON; THERMAL BUDGET PROCESS; VIRTUAL SUBSTRATE;

CMOS INTEGRATED CIRCUITS;

EID: 33646078923     PISSN: 00406090     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.tsf.2005.07.347     Document Type: Article

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