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Volumn 2005, Issue , 2005, Pages 401-406

In-line voltage contrast inspection of ungrounded chain test structures for timely and detailed characterization of contact and via yield loss

Author keywords

[No Author keywords available]

Indexed keywords

CHAIN TEST STRUCTURES; IN-LINE VC INSPECTION; VOLTAGE CONTRAST INSPECTION;

EID: 33645692905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (9)
  • 1
    • 0242516890 scopus 로고    scopus 로고
    • Real time fault site isolation of front-end defects in ULSI-ESRAM utilizing in-line passive voltage contrast analysis
    • Nov
    • O. D. Patterson, J. L. Drown, B. D. Crevasse, A. Salah, K. K. Harris, "Real Time Fault Site Isolation of Front-end Defects in ULSI-ESRAM Utilizing In-Line Passive Voltage Contrast Analysis", Proceedings of ISTFA, Nov 2002, pp. 591-599.
    • (2002) Proceedings of ISTFA , pp. 591-599
    • Patterson, O.D.1    Drown, J.L.2    Crevasse, B.D.3    Salah, A.4    Harris, K.K.5
  • 2
    • 1542360788 scopus 로고    scopus 로고
    • Passive voltage contrast technique for rapid in-line characterization and failure isolation during development of deep-submicron ASIC CMOS technology
    • Nov
    • V. Liang, H. Sur, S. Bothra, "Passive Voltage Contrast Technique for Rapid In-line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology", Proceedings of ISTFA, Nov 1998, pp. 221-225.
    • (1998) Proceedings of ISTFA , pp. 221-225
    • Liang, V.1    Sur, H.2    Bothra, S.3
  • 4
    • 1542300926 scopus 로고    scopus 로고
    • An application of Passive Voltage Contrast (PVC) to failure analysis of CMOS LSI using secondary electron collection
    • A. Nishikawa, N. Kato, Y. Kohno, N. Miura, M. Shimizu, "An Application of Passive Voltage Contrast (PVC) to Failure Analysis of CMOS LSI Using Secondary Electron Collection", Proceedings of ISTFA, 1999, pp. 239-243.
    • (1999) Proceedings of ISTFA , pp. 239-243
    • Nishikawa, A.1    Kato, N.2    Kohno, Y.3    Miura, N.4    Shimizu, M.5
  • 5
    • 0031199689 scopus 로고    scopus 로고
    • Microelectronic test structures for rapid automated contactless inline defect inspection
    • A. V. S. Satya, "Microelectronic Test Structures for Rapid Automated Contactless Inline Defect Inspection", IEEE Trans. Semi. Manuf., Vol. 10, No. 3 (1997), pp. 384-389.
    • (1997) IEEE Trans. Semi. Manuf. , vol.10 , Issue.3 , pp. 384-389
    • Satya, A.V.S.1
  • 6
    • 33645665785 scopus 로고    scopus 로고
    • Rapid reduction of poly-silicon electrical DO using uLoop test structures
    • Mar
    • O. D. Patterson, B. D. Crevasse, K. K. Harris, G. W. Cochran, "Rapid Reduction of Poly-Silicon Electrical DO using uLoop Test Structures", Proceedings of ASMC, pp. 266-272, Mar 2003.
    • (2003) Proceedings of ASMC , pp. 266-272
    • Patterson, O.D.1    Crevasse, B.D.2    Harris, K.K.3    Cochran, G.W.4
  • 9
    • 33645664367 scopus 로고    scopus 로고
    • Application of uLoop™ method to killer defect detection and in-line monitoring for FEOL process of 90nm-node logic device
    • A. Shimada, Y. Matsumiya, A. Fushida, A. Shimizu, "Application of uLoop™ Method to Killer Defect Detection and In-line Monitoring for FEOL Process of 90nm-node Logic Device", Proceedings of ISSM, 2004.
    • (2004) Proceedings of ISSM
    • Shimada, A.1    Matsumiya, Y.2    Fushida, A.3    Shimizu, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.