Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 1998, Pages 221-225

  Liang, V ^a   Sur, H ^a   Bothra, S ^a  

^a PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL PROBING; PASSIVE VOLTAGE CONTRAST TECHNIQUES (PVC);

CMOS INTEGRATED CIRCUITS; COMPOSITION; ELECTRON BEAMS; LITHOGRAPHY; PH EFFECTS; PLASMA APPLICATIONS; PROBLEM SOLVING; SCANNING ELECTRON MICROSCOPY; SOLVENTS; VAPOR DEPOSITION;

ELECTRIC POTENTIAL;

EID: 1542360788     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. J. Colvin, EOS/ESD Symposium Proceedings, 173-176 (1990)
2. S. Bothra, H. Sur, V. Liang, IRPS Proceedings, 150-156 (1998)